1089 lines
126 KiB
Plaintext
1089 lines
126 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.884209 # Number of seconds simulated
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sim_ticks 1884208734500 # Number of ticks simulated
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final_tick 1884208734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 147223 # Simulator instruction rate (inst/s)
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host_op_rate 147223 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4942377286 # Simulator tick rate (ticks/s)
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host_mem_usage 320260 # Number of bytes of host memory used
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host_seconds 381.24 # Real time elapsed on the host
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sim_insts 56126572 # Number of instructions simulated
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sim_ops 56126572 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 25914048 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28566400 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7560448 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7560448 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 404907 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 446350 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 118132 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 118132 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 13753279 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 1407674 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 15160953 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 558749 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 558749 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4012532 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4012532 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4012532 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 13753279 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 1407674 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 19173485 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 446350 # Number of read requests accepted
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system.physmem.writeReqs 118132 # Number of write requests accepted
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system.physmem.readBursts 446350 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 118132 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 28559040 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7558400 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 28566400 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7560448 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 28089 # Per bank write bursts
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system.physmem.perBankRdBursts::1 28219 # Per bank write bursts
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system.physmem.perBankRdBursts::2 28571 # Per bank write bursts
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system.physmem.perBankRdBursts::3 28273 # Per bank write bursts
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system.physmem.perBankRdBursts::4 27775 # Per bank write bursts
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system.physmem.perBankRdBursts::5 27529 # Per bank write bursts
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system.physmem.perBankRdBursts::6 27274 # Per bank write bursts
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system.physmem.perBankRdBursts::7 26987 # Per bank write bursts
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system.physmem.perBankRdBursts::8 27827 # Per bank write bursts
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system.physmem.perBankRdBursts::9 27514 # Per bank write bursts
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system.physmem.perBankRdBursts::10 28065 # Per bank write bursts
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system.physmem.perBankRdBursts::11 27430 # Per bank write bursts
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system.physmem.perBankRdBursts::12 27510 # Per bank write bursts
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system.physmem.perBankRdBursts::13 28401 # Per bank write bursts
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system.physmem.perBankRdBursts::14 28311 # Per bank write bursts
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system.physmem.perBankRdBursts::15 28460 # Per bank write bursts
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system.physmem.perBankWrBursts::0 7814 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7677 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8054 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7732 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7319 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6955 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6788 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6406 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7235 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6877 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7390 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6865 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7046 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8008 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7991 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7943 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
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system.physmem.totGap 1884200137500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 446350 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 118132 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 402858 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 3909 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2828 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1301 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2032 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 4354 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 3963 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 2519 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 2152 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 2122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 2100 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1643 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1621 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 1850 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 2123 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 1201 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 877 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1024 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1062 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 4664 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::18 4781 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4804 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4807 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4824 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::22 4947 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5088 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::24 5171 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 5379 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::26 5611 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 5560 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::28 5729 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 5781 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5861 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5917 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 907 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::35 954 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::36 875 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 993 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::39 1067 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 976 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 1137 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 1161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1136 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1209 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1384 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 1615 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1837 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 2004 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 1906 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 1810 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::51 1674 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 1668 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::53 1785 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 1617 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 827 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 369 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65499 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 551.419716 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 340.219574 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 417.619626 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 14326 21.87% 21.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10638 16.24% 38.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5049 7.71% 45.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3016 4.60% 50.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2484 3.79% 54.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2116 3.23% 57.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1384 2.11% 59.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1595 2.44% 62.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 24891 38.00% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 65499 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 6964 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 64.074383 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 16.502018 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 2530.928651 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-8191 6961 99.96% 99.96% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 6964 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 6964 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 16.958644 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 16.733261 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 3.741198 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::16 5665 81.35% 81.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 36 0.52% 81.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 854 12.26% 94.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 55 0.79% 94.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 10 0.14% 95.06% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 13 0.19% 95.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::22 23 0.33% 95.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::23 94 1.35% 96.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 12 0.17% 97.10% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 41 0.59% 97.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 13 0.19% 97.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 17 0.24% 98.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 13 0.19% 98.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 12 0.17% 98.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 3 0.04% 98.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::31 21 0.30% 98.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 7 0.10% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::33 2 0.03% 98.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::34 2 0.03% 98.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::35 1 0.01% 98.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36 2 0.03% 99.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::37 3 0.04% 99.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::38 3 0.04% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::39 2 0.03% 99.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40 8 0.11% 99.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::41 7 0.10% 99.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::43 3 0.04% 99.40% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44 1 0.01% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::45 1 0.01% 99.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::46 1 0.01% 99.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48 2 0.03% 99.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::50 1 0.01% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::51 1 0.01% 99.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52 4 0.06% 99.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56 9 0.13% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::57 8 0.11% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::58 4 0.06% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 6964 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 7297586750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 15664493000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2231175000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 16353.69 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 35103.69 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 15.16 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.15 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 22.97 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 402726 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 96110 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.25 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.36 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3337927.76 # Average gap between requests
|
|
system.physmem.pageHitRate 88.39 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 1774702818500 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 62917660000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 46582219000 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.throughput 19215856 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 295757 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 295741 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9619 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9619 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 118132 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 156 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 156 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 158094 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 158094 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887017 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920147 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1044827 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30817728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30862044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 36171164 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 36171164 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 35520 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 29834000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1588295250 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3825084824 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 376625999 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.295855 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1728026399000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.295855 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.080991 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.080991 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21134133 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21134133 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::tsunami.ide 12414876231 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 12414876231 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 12436010364 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 12436010364 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 12436010364 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 12436010364 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122162.618497 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 122162.618497 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 298779.270095 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 298779.270095 # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 298046.982960 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 298046.982960 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 364154 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 28275 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 12.879010 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137133 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12137133 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10251971233 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 10251971233 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 10264108366 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 10264108366 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 10264108366 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 10264108366 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70156.838150 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 70156.838150 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246726.300371 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 246726.300371 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 14968340 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 12984271 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 377638 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 10101234 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 5190890 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 51.388672 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 808188 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 32062 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9240282 # DTB read hits
|
|
system.cpu.dtb.read_misses 17901 # DTB read misses
|
|
system.cpu.dtb.read_acv 211 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 766280 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6385567 # DTB write hits
|
|
system.cpu.dtb.write_misses 2310 # DTB write misses
|
|
system.cpu.dtb.write_acv 159 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 298488 # DTB write accesses
|
|
system.cpu.dtb.data_hits 15625849 # DTB hits
|
|
system.cpu.dtb.data_misses 20211 # DTB misses
|
|
system.cpu.dtb.data_acv 370 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1064768 # DTB accesses
|
|
system.cpu.itb.fetch_hits 4001359 # ITB hits
|
|
system.cpu.itb.fetch_misses 6809 # ITB misses
|
|
system.cpu.itb.fetch_acv 657 # ITB acv
|
|
system.cpu.itb.fetch_accesses 4008168 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 176815826 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 56126572 # Number of instructions committed
|
|
system.cpu.committedOps 56126572 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 2538059 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 5497 # Number of times Execute suspended instruction fetching
|
|
system.cpu.quiesceCycles 3593513250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.cpi 3.150305 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.317430 # IPC: instructions per cycle
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211465 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105856 57.95% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 148872 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1833844528000 97.33% 97.33% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 80077500 0.00% 97.33% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 673181000 0.04% 97.37% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 49609971000 2.63% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1884207757500 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.693584 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.814956 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175516 91.22% 93.43% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192403 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1735 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1905
|
|
system.cpu.kern.mode_good::user 1735
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.324587 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.080952 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 36214076000 1.92% 1.92% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 4058025000 0.22% 2.14% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1843935646500 97.86% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
|
system.cpu.tickCycles 85802593 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 91013233 # Total number of cycles that the object has spent stopped
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.iobus.throughput 1436106 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51171 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 51171 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 2705924 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 380105365 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 43180001 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 1458006 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 509.628197 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 18953120 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1458517 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 12.994789 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 31559763000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 509.628197 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.995368 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.995368 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 21870509 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 21870509 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 18953123 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 18953123 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 18953123 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 18953123 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 18953123 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 18953123 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1458693 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1458693 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1458693 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1458693 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1458693 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1458693 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20024605540 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 20024605540 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 20024605540 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 20024605540 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 20024605540 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 20024605540 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 20411816 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 20411816 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 20411816 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 20411816 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 20411816 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 20411816 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071463 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.071463 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.071463 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.071463 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.071463 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.071463 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.772424 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13727.772424 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13727.772424 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13727.772424 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458693 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1458693 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1458693 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1458693 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1458693 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1458693 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17099831460 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 17099831460 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17099831460 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 17099831460 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17099831460 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 17099831460 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071463 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.071463 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.071463 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.707561 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.707561 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 125457945 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2557417 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2557383 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 838210 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 345773 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 304222 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917325 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663192 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 6580517 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352448 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143032604 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 236385052 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 236375068 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 13888 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2697678498 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2191733540 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2194708666 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 339421 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65326.541432 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2981708 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 404583 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 7.369830 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 54488.510247 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10838.031185 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.831429 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165375 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996804 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5155 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 30250697 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 30250697 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2261599 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2261599 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 838210 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 838210 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 187541 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 187541 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2449140 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2449140 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2449140 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2449140 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 288654 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.inst 18 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 116680 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 116680 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 405334 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 405334 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 405334 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 405334 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918477985 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18918477985 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8091487855 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8091487855 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 27009965840 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 27009965840 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 27009965840 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 27009965840 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550253 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2550253 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 838210 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 838210 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 22 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304221 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 304221 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 2854474 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2854474 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 2854474 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2854474 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113186 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.113186 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.818182 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383537 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383537 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142000 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.142000 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142000 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.142000 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65540.328507 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65540.328507 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11916.500000 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11916.500000 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69347.684736 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69347.684736 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66636.319282 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 66636.319282 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66636.319282 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 66636.319282 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 76620 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 76620 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288654 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 18 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116680 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 116680 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 405334 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 405334 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 405334 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 405334 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309737015 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309737015 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 281515 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 281515 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6590751145 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6590751145 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21900488160 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 21900488160 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21900488160 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 21900488160 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333191500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333191500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887604500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887604500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3220796000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3220796000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113186 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113186 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.818182 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383537 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383537 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142000 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.142000 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142000 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.142000 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53038.367786 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53038.367786 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15639.722222 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15639.722222 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.697163 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.697163 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54030.720739 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54030.720739 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54030.720739 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54030.720739 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1395313 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.982337 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 13766743 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1395825 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 9.862800 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982337 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.999966 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999966 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 63632966 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 63632966 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.inst 7808132 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7808132 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.inst 5576867 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 5576867 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182710 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 182710 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.inst 13384999 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13384999 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.inst 13384999 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13384999 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.inst 1201593 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1201593 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.inst 573675 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 573675 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17309 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.inst 1775268 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1775268 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.inst 1775268 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1775268 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31027712510 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 31027712510 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20753893806 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 20753893806 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231648000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 231648000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.inst 51781606316 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 51781606316 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.inst 51781606316 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 51781606316 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 9009725 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 9009725 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 6150542 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6150542 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200019 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 200019 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.inst 15160267 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15160267 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.inst 15160267 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15160267 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133366 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.133366 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093272 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.093272 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086537 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086537 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.117100 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.117100 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.117100 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.117100 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25822.148190 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 25822.148190 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36177.092964 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 36177.092964 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.095499 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.095499 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29168.331945 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 29168.331945 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29168.331945 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 29168.331945 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 838210 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 838210 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127240 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 127240 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269470 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 269470 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 396710 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 396710 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 396710 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 396710 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074353 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1074353 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304205 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 304205 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17306 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17306 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 1378558 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1378558 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 1378558 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1378558 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26912219745 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26912219745 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10275413589 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10275413589 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196866500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196866500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37187633334 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 37187633334 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37187633334 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 37187633334 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423283000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423283000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003033000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003033000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426316000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426316000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119244 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119244 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049460 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049460 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086522 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086522 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.090932 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.090932 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25049.699442 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25049.699442 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33777.924719 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33777.924719 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11375.621172 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.621172 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|