2c9ca672df
This patch includes a rather substantial change to the memory controller profiler in order to work with the new configuration system. Most noteably, the mem_cntrl_profiler no longer uses a string map, but instead a vector. Eventually this support should be removed from the main profiler and go into a separate object. Each memory controller should have a pointer to that new mem_cntrl profile object.
216 lines
7.9 KiB
Python
216 lines
7.9 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../common')
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parser = optparse.OptionParser()
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parser.add_option("-a", "--atomic", action="store_true",
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help="Use atomic (non-timing) mode")
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parser.add_option("-b", "--blocking", action="store_true",
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help="Use blocking caches")
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parser.add_option("-l", "--maxloads", metavar="N", default=0,
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help="Stop after N loads")
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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metavar="T",
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help="Stop after T ticks")
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parser.add_option("-t", "--testers", type="int", metavar="N", default=1,
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help="number of testers/cores")
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parser.add_option("-f", "--functional", type="int", default=0,
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metavar="PCT",
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help="Target percentage of functional accesses "
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"[default: %default]")
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parser.add_option("-u", "--uncacheable", type="int", default=0,
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metavar="PCT",
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help="Target percentage of uncacheable accesses "
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"[default: %default]")
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parser.add_option("--progress", type="int", default=1000,
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metavar="NLOADS",
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help="Progress message interval "
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"[default: %default]")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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block_size = 64
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if options.testers > block_size:
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print "Error: Number of testers %d limited to %d because of false sharing" \
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% (options.testers, block_size)
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sys.exit(1)
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cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, \
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percent_functional=options.functional, \
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percent_uncacheable=options.uncacheable, \
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progress_interval=options.progress) \
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for i in xrange(options.testers) ]
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system = System(cpu = cpus,
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funcmem = PhysicalMemory(),
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physmem = PhysicalMemory())
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class L1Cache(RubyCache):
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assoc = 2
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latency = 3
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size = 32768
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class L2Cache(RubyCache):
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assoc = 16
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latency = 15
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size = 1048576
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for (i, cpu) in enumerate(cpus):
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#
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# First create the Ruby objects associated with this cpu
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# Eventually this code should go in a python file specific to the
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# MOESI_hammer protocol
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#
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l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
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l1i_cache = L1Cache(cache_profiler = l1i_profiler)
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l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i))
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l1d_cache = L1Cache(cache_profiler = l1d_profiler)
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l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i))
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l2_cache = L2Cache(cache_profiler = l2_profiler)
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cpu_seq = RubySequencer(icache = l1i_cache,
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dcache = l1d_cache,
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funcmem_port = system.physmem.port)
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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L2cacheMemory = l2_cache)
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mem_cntrl = RubyMemoryControl(version = i)
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dir_cntrl = Directory_Controller(version = i,
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directory = RubyDirectoryMemory(),
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memBuffer = mem_cntrl)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = DMASequencer())
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#
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# As noted above: Two independent list are track to maintain the order of
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# nodes/controllers assumed by the ruby network
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#
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l1_cntrl_nodes.append(l1_cntrl)
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dir_cntrl_nodes.append(dir_cntrl)
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dma_cntrl_nodes.append(dma_cntrl)
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#
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# Finally tie the memtester ports to the correct system ports
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#
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cpu.test = cpu_seq.port
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cpu.functional = system.funcmem.port
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#
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# Important: the topology constructor must be called before the network
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# constructor.
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#
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network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes))
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mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
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for dir_cntrl in dir_cntrl_nodes])
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#
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# determine the number of memory controllers and other memory controller
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# parameters for the profiler
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#
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mcCount = len(dir_cntrl_nodes)
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banksPerRank = dir_cntrl_nodes[0].memBuffer.banks_per_rank
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ranksPerDimm = dir_cntrl_nodes[0].memBuffer.ranks_per_dimm
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dimmsPerChannel = dir_cntrl_nodes[0].memBuffer.dimms_per_channel
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ruby_profiler = RubyProfiler(mem_cntrl_count = mcCount,
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banks_per_rank = banksPerRank,
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ranks_per_dimm = ranksPerDimm,
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dimms_per_channel = dimmsPerChannel)
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system.ruby = RubySystem(clock = '1GHz',
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network = network,
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profiler = ruby_profiler,
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tracer = RubyTracer(),
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debug = RubyDebug(filter_string = 'none',
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verbosity_string = 'none',
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protocol_trace = False),
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mem_size_mb = mem_size_mb)
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( system = system )
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if options.atomic:
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root.system.mem_mode = 'atomic'
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else:
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate(root)
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# simulate until program terminates
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exit_event = m5.simulate(options.maxtick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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