1348 lines
158 KiB
Plaintext
1348 lines
158 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 2.902619 # Number of seconds simulated
|
|
sim_ticks 2902619131000 # Number of ticks simulated
|
|
final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 744858 # Simulator instruction rate (inst/s)
|
|
host_op_rate 898074 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 19216925045 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 553548 # Number of bytes of host memory used
|
|
host_seconds 151.05 # Real time elapsed on the host
|
|
sim_insts 112506996 # Number of instructions simulated
|
|
sim_ops 135649573 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory
|
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 168277 # Number of read requests accepted
|
|
system.physmem.writeReqs 122785 # Number of write requests accepted
|
|
system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 10195464 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 7595380 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 4505 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 9709 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 9253 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 10215 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 10266 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 18988 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 10225 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 10580 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 10353 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 9698 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 9938 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 9924 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 8855 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 9985 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 10410 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 9933 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 9763 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 7210 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 6831 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 8029 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 7890 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 7400 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 7418 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 7750 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 7625 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 7363 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 7566 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 7503 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 6751 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 7436 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 7741 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 7101 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 2902618699500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 158705 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 118404 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 167256 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 571 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 2070 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 2628 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 6016 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 6156 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 6193 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 6817 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 7564 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 8052 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 8864 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 8233 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 7730 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 7142 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 6957 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 6255 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 6112 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 6123 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 6074 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 239 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 234 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 123 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 70 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 20.279379 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.638132 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 12.466375 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 5064 86.37% 86.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 42 0.72% 87.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 33 0.56% 87.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 216 3.68% 91.34% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 215 3.67% 95.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 12 0.20% 95.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 16 0.27% 95.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 25 0.43% 96.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 3 0.05% 96.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 6 0.10% 96.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 4 0.07% 96.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 164 2.80% 99.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 4 0.07% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 3 0.05% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 2 0.03% 99.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 13 0.22% 99.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 5 0.09% 99.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 1 0.02% 99.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 3 0.05% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 3 0.05% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1491787750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 138438 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 90000 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 9972509.98 # Average gap between requests
|
|
system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 96924620000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 669.480430 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 669.392372 # Core power per rank (mW)
|
|
system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.trans_dist::ReadReq 70650 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 70650 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27618 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27618 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 82180 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 219 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 281834 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 281834 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 24532668 # DTB read hits
|
|
system.cpu.dtb.read_misses 8148 # DTB read misses
|
|
system.cpu.dtb.write_hits 19614514 # DTB write hits
|
|
system.cpu.dtb.write_misses 1410 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 24540816 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 19615924 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 44147182 # DTB hits
|
|
system.cpu.dtb.misses 9558 # DTB misses
|
|
system.cpu.dtb.accesses 44156740 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 115605897 # ITB inst hits
|
|
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 115610659 # ITB inst accesses
|
|
system.cpu.itb.hits 115605897 # DTB hits
|
|
system.cpu.itb.misses 4762 # DTB misses
|
|
system.cpu.itb.accesses 115610659 # DTB accesses
|
|
system.cpu.numCycles 5805238262 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 112506996 # Number of instructions committed
|
|
system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
|
|
system.cpu.num_func_calls 9898964 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 119948924 # number of integer instructions
|
|
system.cpu.num_fp_insts 11161 # number of float instructions
|
|
system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 45428231 # number of memory refs
|
|
system.cpu.num_load_insts 24855392 # Number of load instructions
|
|
system.cpu.num_store_insts 20572839 # Number of store instructions
|
|
system.cpu.num_idle_cycles 5386456122.024144 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.927861 # Percentage of idle cycles
|
|
system.cpu.Branches 25929456 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 138771626 # Class of executed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
|
|
system.cpu.icache.tags.replacements 1699818 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 117306233 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 117306233 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 113905561 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 113905561 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 113905561 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 113905561 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 113905561 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 113905561 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1700336 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1700336 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1700336 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1700336 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23243215000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 23243215000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 23243215000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 23243215000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 23243215000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 23243215000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 115605897 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 115605897 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 115605897 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 115605897 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 115605897 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 115605897 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13669.777620 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13669.777620 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.777620 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13669.777620 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1700336 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835992000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 19835992000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.924852 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 88869 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 64932.369340 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2760846 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 154135 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 17.911869 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822165 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809354 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012212 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724019 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001590 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.773221 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146190 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.071320 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.990789 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 26241966 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 26241966 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7097 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3700 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1682273 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 514822 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2207892 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 686231 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 686231 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 166049 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 166049 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7097 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3700 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1682273 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 680871 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2373941 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7097 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3700 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1682273 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 680871 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2373941 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 18039 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 12191 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 30239 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130235 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 130235 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 18039 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 142426 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 160474 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 18039 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 142426 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 160474 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 567750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1312883000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 918689000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2232289250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 527013 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2238131 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 686231 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 686231 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2742 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2742 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 296284 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 296284 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7104 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3702 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1700312 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 823297 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2534415 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7104 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3702 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1700312 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 823297 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2534415 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000985 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000540 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010609 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023132 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.013511 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991612 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991612 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439561 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.439561 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000985 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000540 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010609 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.172995 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.063318 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000985 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000540 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010609 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.172995 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.063318 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72780.253894 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75357.968994 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73821.530143 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 82180 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 82180 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18039 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12191 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 30239 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2719 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2719 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130235 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130235 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 18039 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 142426 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 160474 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18039 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 142426 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 160474 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 480750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1087047500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766535000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1854188250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023132 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013511 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991612 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991612 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439561 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439561 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063318 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60260.962359 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62877.122467 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61317.776712 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 822747 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 43252597 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 823259 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 52.538262 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 177194873 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 177194873 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23122385 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23122385 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 18831357 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 18831357 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 41953742 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 41953742 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 42345863 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 42345863 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 402167 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 402167 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 820348 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 42654935 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 42654935 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 43166211 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 43166211 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 686231 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 686231 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401540 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 401540 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 52963 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36424 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.070837 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328122 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
|
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 234 # number of overall misses
|
|
system.iocache.overall_misses::total 234 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 28038377 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 28038377 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 28038377 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 28038377 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 28038377 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 28038377 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 119822.123932 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 119822.123932 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 119822.123932 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 36224 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 15869377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 15869377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2206856981 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2206856981 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 15869377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 15869377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 15869377 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 15869377 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|