Yasuko Eckert 2c293823aa cpu: add a condition-code register class ... Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.		2013-10-15 14:22:44 -04:00
..
branch.hh	ARM: Clean up condCodes in IT blocks.	2012-03-21 10:34:06 -05:00
macromem.cc	arm: set ldr_ret_uop as conditional or unconditional control	2013-04-17 16:07:10 -05:00
macromem.hh	ARM: Fix RFE macrop.	2011-03-17 19:20:19 -05:00
mem.cc	ARM: Make some of the trace code more compact	2010-06-02 12:58:18 -05:00
mem.hh	ARM: Fix RFE macrop.	2011-03-17 19:20:19 -05:00
misc.cc	cpu: rename *_DepTag constants to *_Reg_Base	2013-10-15 14:22:43 -04:00
misc.hh	ARM: Make undefined instructions obey predication.	2010-06-02 12:58:16 -05:00
mult.hh	ARM: Add base classes for multiply instructions.	2010-06-02 12:58:03 -05:00
pred_inst.cc	ARM: Get rid of obsoleted predicated inst formats, etc.	2010-06-02 12:58:02 -05:00
pred_inst.hh	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	2011-01-18 16:30:05 -06:00
static_inst.cc	cpu: add a condition-code register class	2013-10-15 14:22:44 -04:00
static_inst.hh	Merge with head, hopefully the last time for this batch.	2012-01-31 22:40:08 -08:00
vfp.cc	cpu: rename *_DepTag constants to *_Reg_Base	2013-10-15 14:22:43 -04:00
vfp.hh	ARM: fix bits-to-fp conversion function declarations.	2012-03-01 17:26:30 -06:00