eb0e416998
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
166 lines
5 KiB
C++
166 lines
5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Ali Saidi
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*/
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#include <string>
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#include "arch/alpha/ev5.hh"
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#include "arch/alpha/vtophys.hh"
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#include "base/chunk_generator.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "mem/vport.hh"
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using namespace std;
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using namespace AlphaISA;
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AlphaISA::PageTableEntry
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AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
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{
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Addr level1_pte = ptbr + vaddr.level1();
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AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
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if (!level1.valid()) {
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DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
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return 0;
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}
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Addr level2_pte = level1.paddr() + vaddr.level2();
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AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
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if (!level2.valid()) {
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DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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Addr level3_pte = level2.paddr() + vaddr.level3();
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AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
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if (!level3.valid()) {
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DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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return level3;
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}
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Addr
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AlphaISA::vtophys(Addr vaddr)
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{
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Addr paddr = 0;
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if (AlphaISA::IsUSeg(vaddr))
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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else if (AlphaISA::IsK0Seg(vaddr))
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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else
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panic("vtophys: ptbr is not set on virtual lookup");
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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Addr
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AlphaISA::vtophys(ThreadContext *tc, Addr addr)
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{
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AlphaISA::VAddr vaddr = addr;
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Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
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Addr paddr = 0;
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//@todo Andrew couldn't remember why he commented some of this code
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//so I put it back in. Perhaps something to do with gdb debugging?
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if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
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paddr = vaddr & ~ULL(1);
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} else {
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if (AlphaISA::IsK0Seg(vaddr)) {
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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} else if (!ptbr) {
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paddr = vaddr;
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} else {
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AlphaISA::PageTableEntry pte =
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kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
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if (pte.valid())
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paddr = pte.paddr() | vaddr.offset();
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}
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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void
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AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
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{
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uint8_t *dst = (uint8_t *)dest;
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VirtualPort *vp = tc->getVirtPort(tc);
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vp->readBlob(src, dst, cplen);
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tc->delVirtPort(vp);
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}
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void
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AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
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{
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uint8_t *src = (uint8_t *)source;
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VirtualPort *vp = tc->getVirtPort(tc);
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vp->writeBlob(dest, src, cplen);
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tc->delVirtPort(vp);
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}
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void
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AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
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{
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int len = 0;
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VirtualPort *vp = tc->getVirtPort(tc);
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do {
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vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
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len++;
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} while (len < maxlen && dst[len] != 0 );
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tc->delVirtPort(vp);
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dst[len] = 0;
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}
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void
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AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
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{
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VirtualPort *vp = tc->getVirtPort(tc);
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for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
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gen.next())
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{
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vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
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src += gen.size();
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}
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tc->delVirtPort(vp);
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}
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