2ac04c11ac
This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables).
258 lines
8.1 KiB
C++
258 lines
8.1 KiB
C++
/*
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* Copyright (c) 2014 Advanced Micro Devices, Inc.
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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/**
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* @file
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* Declarations of a non-full system Page Table.
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*/
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#ifndef __MEM_PAGE_TABLE_HH__
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#define __MEM_PAGE_TABLE_HH__
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#include <string>
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#include <unordered_map>
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#include "arch/isa_traits.hh"
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#include "arch/tlb.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "mem/request.hh"
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#include "sim/serialize.hh"
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#include "sim/system.hh"
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class ThreadContext;
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/**
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* Declaration of base class for page table
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*/
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class PageTableBase : public Serializable
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{
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protected:
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struct cacheElement {
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bool valid;
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Addr vaddr;
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TheISA::TlbEntry entry;
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};
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struct cacheElement pTableCache[3];
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const Addr pageSize;
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const Addr offsetMask;
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const uint64_t pid;
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const std::string _name;
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public:
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PageTableBase(const std::string &__name, uint64_t _pid,
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Addr _pageSize = TheISA::PageBytes)
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: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
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pid(_pid), _name(__name)
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{
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assert(isPowerOf2(pageSize));
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pTableCache[0].valid = false;
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pTableCache[1].valid = false;
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pTableCache[2].valid = false;
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}
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virtual ~PageTableBase() {};
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/* generic page table mapping flags
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* unset | set
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* bit 0 - no-clobber | clobber
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* bit 1 - present | not-present
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* bit 2 - cacheable | uncacheable
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* bit 3 - read-write | read-only
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*/
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enum MappingFlags : uint32_t {
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Clobber = 1,
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NotPresent = 2,
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Uncacheable = 4,
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ReadOnly = 8,
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};
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virtual void initState(ThreadContext* tc) = 0;
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// for DPRINTF compatibility
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const std::string name() const { return _name; }
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Addr pageAlign(Addr a) { return (a & ~offsetMask); }
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Addr pageOffset(Addr a) { return (a & offsetMask); }
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/**
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* Maps a virtual memory region to a physical memory region.
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* @param vaddr The starting virtual address of the region.
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* @param paddr The starting physical address where the region is mapped.
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* @param size The length of the region.
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* @param flags Generic mapping flags that can be set by or-ing values
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* from MappingFlags enum.
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*/
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virtual void map(Addr vaddr, Addr paddr, int64_t size,
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uint64_t flags = 0) = 0;
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virtual void remap(Addr vaddr, int64_t size, Addr new_vaddr) = 0;
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virtual void unmap(Addr vaddr, int64_t size) = 0;
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/**
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* Check if any pages in a region are already allocated
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* @param vaddr The starting virtual address of the region.
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* @param size The length of the region.
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* @return True if no pages in the region are mapped.
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*/
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virtual bool isUnmapped(Addr vaddr, int64_t size) = 0;
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/**
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* Lookup function
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* @param vaddr The virtual address.
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* @return entry The page table entry corresponding to vaddr.
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*/
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virtual bool lookup(Addr vaddr, TheISA::TlbEntry &entry) = 0;
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/**
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* Translate function
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* @param vaddr The virtual address.
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* @param paddr Physical address from translation.
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* @return True if translation exists
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*/
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bool translate(Addr vaddr, Addr &paddr);
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/**
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* Simplified translate function (just check for translation)
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* @param vaddr The virtual address.
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* @return True if translation exists
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*/
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bool translate(Addr vaddr) { Addr dummy; return translate(vaddr, dummy); }
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/**
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* Perform a translation on the memory request, fills in paddr
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* field of req.
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* @param req The memory request.
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*/
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Fault translate(RequestPtr req);
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/**
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* Update the page table cache.
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* @param vaddr virtual address (page aligned) to check
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* @param pte page table entry to return
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*/
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inline void updateCache(Addr vaddr, TheISA::TlbEntry entry)
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{
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pTableCache[2].entry = pTableCache[1].entry;
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pTableCache[2].vaddr = pTableCache[1].vaddr;
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pTableCache[2].valid = pTableCache[1].valid;
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pTableCache[1].entry = pTableCache[0].entry;
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pTableCache[1].vaddr = pTableCache[0].vaddr;
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pTableCache[1].valid = pTableCache[0].valid;
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pTableCache[0].entry = entry;
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pTableCache[0].vaddr = vaddr;
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pTableCache[0].valid = true;
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}
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/**
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* Erase an entry from the page table cache.
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* @param vaddr virtual address (page aligned) to check
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*/
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inline void eraseCacheEntry(Addr vaddr)
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{
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// Invalidate cached entries if necessary
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if (pTableCache[0].valid && pTableCache[0].vaddr == vaddr) {
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pTableCache[0].valid = false;
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} else if (pTableCache[1].valid && pTableCache[1].vaddr == vaddr) {
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pTableCache[1].valid = false;
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} else if (pTableCache[2].valid && pTableCache[2].vaddr == vaddr) {
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pTableCache[2].valid = false;
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}
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}
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};
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/**
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* Declaration of functional page table.
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*/
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class FuncPageTable : public PageTableBase
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{
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private:
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typedef std::unordered_map<Addr, TheISA::TlbEntry> PTable;
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typedef PTable::iterator PTableItr;
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PTable pTable;
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public:
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FuncPageTable(const std::string &__name, uint64_t _pid,
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Addr _pageSize = TheISA::PageBytes);
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~FuncPageTable();
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void initState(ThreadContext* tc) override
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{
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}
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void map(Addr vaddr, Addr paddr, int64_t size,
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uint64_t flags = 0) override;
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void remap(Addr vaddr, int64_t size, Addr new_vaddr) override;
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void unmap(Addr vaddr, int64_t size) override;
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/**
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* Check if any pages in a region are already allocated
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* @param vaddr The starting virtual address of the region.
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* @param size The length of the region.
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* @return True if no pages in the region are mapped.
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*/
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bool isUnmapped(Addr vaddr, int64_t size) override;
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/**
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* Lookup function
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* @param vaddr The virtual address.
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* @return entry The page table entry corresponding to vaddr.
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*/
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bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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};
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/**
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* Faux page table class indended to stop the usage of
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* an architectural page table, when there is none defined
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* for a particular ISA.
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*/
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class NoArchPageTable : public FuncPageTable
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{
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public:
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NoArchPageTable(const std::string &__name, uint64_t _pid, System *_sys,
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Addr _pageSize = TheISA::PageBytes) : FuncPageTable(__name, _pid)
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{
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fatal("No architectural page table defined for this ISA.\n");
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}
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};
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#endif // __MEM_PAGE_TABLE_HH__
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