2ac04c11ac
This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables).
426 lines
13 KiB
C++
426 lines
13 KiB
C++
/*
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Andreas Sandberg
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*/
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#ifndef __DEV_DMA_DEVICE_HH__
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#define __DEV_DMA_DEVICE_HH__
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#include <deque>
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#include <memory>
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#include "base/circlebuf.hh"
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#include "dev/io_device.hh"
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#include "params/DmaDevice.hh"
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#include "sim/drain.hh"
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#include "sim/system.hh"
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class DmaPort : public MasterPort, public Drainable
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{
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private:
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/**
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* Take the first packet of the transmit list and attempt to send
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* it as a timing request. If it is successful, schedule the
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* sending of the next packet, otherwise remember that we are
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* waiting for a retry.
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*/
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void trySendTimingReq();
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/**
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* For timing, attempt to send the first item on the transmit
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* list, and if it is successful and there are more packets
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* waiting, then schedule the sending of the next packet. For
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* atomic, simply send and process everything on the transmit
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* list.
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*/
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void sendDma();
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/**
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* Handle a response packet by updating the corresponding DMA
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* request state to reflect the bytes received, and also update
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* the pending request counter. If the DMA request that this
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* packet is part of is complete, then signal the completion event
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* if present, potentially with a delay added to it.
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*
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* @param pkt Response packet to handler
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* @param delay Additional delay for scheduling the completion event
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*/
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void handleResp(PacketPtr pkt, Tick delay = 0);
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struct DmaReqState : public Packet::SenderState
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{
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/** Event to call on the device when this transaction (all packets)
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* complete. */
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Event *completionEvent;
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/** Total number of bytes that this transaction involves. */
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const Addr totBytes;
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/** Number of bytes that have been acked for this transaction. */
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Addr numBytes;
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/** Amount to delay completion of dma by */
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const Tick delay;
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DmaReqState(Event *ce, Addr tb, Tick _delay)
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: completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
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{}
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};
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public:
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/** The device that owns this port. */
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MemObject *const device;
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/** The system that device/port are in. This is used to select which mode
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* we are currently operating in. */
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System *const sys;
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/** Id for all requests */
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const MasterID masterId;
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protected:
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/** Use a deque as we never do any insertion or removal in the middle */
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std::deque<PacketPtr> transmitList;
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/** Event used to schedule a future sending from the transmit list. */
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EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
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/** Number of outstanding packets the dma port has. */
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uint32_t pendingCount;
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/** If the port is currently waiting for a retry before it can
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* send whatever it is that it's sending. */
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bool inRetry;
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protected:
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bool recvTimingResp(PacketPtr pkt) override;
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void recvReqRetry() override;
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void queueDma(PacketPtr pkt);
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public:
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DmaPort(MemObject *dev, System *s);
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RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data, Tick delay, Request::Flags flag = 0);
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bool dmaPending() const { return pendingCount > 0; }
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DrainState drain() override;
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};
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class DmaDevice : public PioDevice
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{
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protected:
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DmaPort dmaPort;
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public:
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typedef DmaDeviceParams Params;
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DmaDevice(const Params *p);
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virtual ~DmaDevice() { }
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void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
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Tick delay = 0)
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{
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dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
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}
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void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
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Tick delay = 0)
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{
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dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
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}
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bool dmaPending() const { return dmaPort.dmaPending(); }
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void init() override;
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unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
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BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID) override;
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};
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/**
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* Buffered DMA engine helper class
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*
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* This class implements a simple DMA engine that feeds a FIFO
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* buffer. The size of the buffer, the maximum number of pending
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* requests and the maximum request size are all set when the engine
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* is instantiated.
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*
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* An <i>asynchronous</i> transfer of a <i>block</i> of data
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* (designated by a start address and a size) is started by calling
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* the startFill() method. The DMA engine will aggressively try to
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* keep the internal FIFO full. As soon as there is room in the FIFO
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* for more data <i>and</i> there are free request slots, a new fill
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* will be started.
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*
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* Data in the FIFO can be read back using the get() and tryGet()
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* methods. Both request a block of data from the FIFO. However, get()
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* panics if the block cannot be satisfied, while tryGet() simply
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* returns false. The latter call makes it possible to implement
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* custom buffer underrun handling.
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*
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* A simple use case would be something like this:
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* \code{.cpp}
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* // Create a DMA engine with a 1KiB buffer. Issue up to 8 concurrent
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* // uncacheable 64 byte (maximum) requests.
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* DmaReadFifo *dma = new DmaReadFifo(port, 1024, 64, 8,
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* Request::UNCACHEABLE);
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*
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* // Start copying 4KiB data from 0xFF000000
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* dma->startFill(0xFF000000, 0x1000);
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*
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* // Some time later when there is data in the FIFO.
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* uint8_t data[8];
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* dma->get(data, sizeof(data))
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* \endcode
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*
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*
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* The DMA engine allows new blocks to be requested as soon as the
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* last request for a block has been sent (i.e., there is no need to
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* wait for pending requests to complete). This can be queried with
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* the atEndOfBlock() method and more advanced implementations may
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* override the onEndOfBlock() callback.
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*/
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class DmaReadFifo : public Drainable, public Serializable
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{
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public:
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DmaReadFifo(DmaPort &port, size_t size,
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unsigned max_req_size,
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unsigned max_pending,
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Request::Flags flags = 0);
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~DmaReadFifo();
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public: // Serializable
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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public: // Drainable
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DrainState drain() override;
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public: // FIFO access
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/**
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* @{
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* @name FIFO access
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*/
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/**
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* Try to read data from the FIFO.
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*
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* This method reads len bytes of data from the FIFO and stores
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* them in the memory location pointed to by dst. The method
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* fails, and no data is written to the buffer, if the FIFO
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* doesn't contain enough data to satisfy the request.
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*
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* @param dst Pointer to a destination buffer
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* @param len Amount of data to read.
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* @return true on success, false otherwise.
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*/
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bool tryGet(uint8_t *dst, size_t len);
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template<typename T>
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bool tryGet(T &value) {
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return tryGet(static_cast<T *>(&value), sizeof(T));
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};
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/**
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* Read data from the FIFO and panic on failure.
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*
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* @see tryGet()
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*
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* @param dst Pointer to a destination buffer
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* @param len Amount of data to read.
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*/
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void get(uint8_t *dst, size_t len);
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template<typename T>
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T get() {
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T value;
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get(static_cast<uint8_t *>(&value), sizeof(T));
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return value;
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};
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/** Get the amount of data stored in the FIFO */
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size_t size() const { return buffer.size(); }
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/** Flush the FIFO */
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void flush() { buffer.flush(); }
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/** @} */
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public: // FIFO fill control
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/**
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* @{
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* @name FIFO fill control
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*/
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/**
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* Start filling the FIFO.
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*
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* @warn It's considered an error to call start on an active DMA
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* engine unless the last request from the active block has been
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* sent (i.e., atEndOfBlock() is true).
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*
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* @param start Physical address to copy from.
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* @param size Size of the block to copy.
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*/
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void startFill(Addr start, size_t size);
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/**
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* Stop the DMA engine.
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*
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* Stop filling the FIFO and ignore incoming responses for pending
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* requests. The onEndOfBlock() callback will not be called after
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* this method has been invoked. However, once the last response
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* has been received, the onIdle() callback will still be called.
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*/
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void stopFill();
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/**
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* Has the DMA engine sent out the last request for the active
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* block?
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*/
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bool atEndOfBlock() const {
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return nextAddr == endAddr;
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}
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/**
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* Is the DMA engine active (i.e., are there still in-flight
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* accesses)?
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*/
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bool isActive() const {
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return !(pendingRequests.empty() && atEndOfBlock());
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}
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/** @} */
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protected: // Callbacks
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/**
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* @{
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* @name Callbacks
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*/
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/**
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* End of block callback
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*
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* This callback is called <i>once</i> after the last access in a
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* block has been sent. It is legal for a derived class to call
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* startFill() from this method to initiate a transfer.
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*/
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virtual void onEndOfBlock() {};
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/**
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* Last response received callback
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*
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* This callback is called when the DMA engine becomes idle (i.e.,
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* there are no pending requests).
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*
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* It is possible for a DMA engine to reach the end of block and
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* become idle at the same tick. In such a case, the
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* onEndOfBlock() callback will be called first. This callback
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* will <i>NOT</i> be called if that callback initiates a new DMA transfer.
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*/
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virtual void onIdle() {};
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/** @} */
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private: // Configuration
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/** Maximum request size in bytes */
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const Addr maxReqSize;
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/** Maximum FIFO size in bytes */
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const size_t fifoSize;
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/** Request flags */
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const Request::Flags reqFlags;
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DmaPort &port;
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private:
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class DmaDoneEvent : public Event
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{
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public:
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DmaDoneEvent(DmaReadFifo *_parent, size_t max_size);
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void kill();
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void cancel();
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bool canceled() const { return _canceled; }
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void reset(size_t size);
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void process();
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bool done() const { return _done; }
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size_t requestSize() const { return _requestSize; }
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const uint8_t *data() const { return _data.data(); }
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uint8_t *data() { return _data.data(); }
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private:
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DmaReadFifo *parent;
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bool _done;
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bool _canceled;
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size_t _requestSize;
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std::vector<uint8_t> _data;
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};
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typedef std::unique_ptr<DmaDoneEvent> DmaDoneEventUPtr;
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/**
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* DMA request done, handle incoming data and issue new
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* request.
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*/
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void dmaDone();
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/** Handle pending requests that have been flagged as done. */
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void handlePending();
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/** Try to issue new DMA requests */
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void resumeFill();
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private: // Internal state
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Fifo<uint8_t> buffer;
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Addr nextAddr;
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Addr endAddr;
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std::deque<DmaDoneEventUPtr> pendingRequests;
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std::deque<DmaDoneEventUPtr> freeRequests;
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};
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#endif // __DEV_DMA_DEVICE_HH__
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