2ac04c11ac
This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables).
364 lines
11 KiB
C++
364 lines
11 KiB
C++
/*
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* Copyright (c) 2012-2013,2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#ifndef __CPU_SIMPLE_TIMING_HH__
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#define __CPU_SIMPLE_TIMING_HH__
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#include "cpu/simple/base.hh"
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#include "cpu/simple/exec_context.hh"
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#include "cpu/translation.hh"
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#include "params/TimingSimpleCPU.hh"
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class TimingSimpleCPU : public BaseSimpleCPU
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{
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public:
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TimingSimpleCPU(TimingSimpleCPUParams * params);
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virtual ~TimingSimpleCPU();
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void init() override;
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private:
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/*
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* If an access needs to be broken into fragments, currently at most two,
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* the the following two classes are used as the sender state of the
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* packets so the CPU can keep track of everything. In the main packet
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* sender state, there's an array with a spot for each fragment. If a
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* fragment has already been accepted by the CPU, aka isn't waiting for
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* a retry, it's pointer is NULL. After each fragment has successfully
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* been processed, the "outstanding" counter is decremented. Once the
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* count is zero, the entire larger access is complete.
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*/
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class SplitMainSenderState : public Packet::SenderState
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{
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public:
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int outstanding;
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PacketPtr fragments[2];
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int
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getPendingFragment()
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{
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if (fragments[0]) {
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return 0;
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} else if (fragments[1]) {
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return 1;
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} else {
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return -1;
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}
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}
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};
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class SplitFragmentSenderState : public Packet::SenderState
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{
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public:
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SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
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bigPkt(_bigPkt), index(_index)
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{}
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PacketPtr bigPkt;
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int index;
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void
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clearFromParent()
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{
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SplitMainSenderState * main_send_state =
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dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
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main_send_state->fragments[index] = NULL;
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}
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};
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class FetchTranslation : public BaseTLB::Translation
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{
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protected:
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TimingSimpleCPU *cpu;
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public:
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FetchTranslation(TimingSimpleCPU *_cpu)
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: cpu(_cpu)
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{}
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void
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markDelayed()
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{
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assert(cpu->_status == BaseSimpleCPU::Running);
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cpu->_status = ITBWaitResponse;
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}
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void
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finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode)
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{
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cpu->sendFetch(fault, req, tc);
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}
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};
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FetchTranslation fetchTranslation;
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void threadSnoop(PacketPtr pkt, ThreadID sender);
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void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
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void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read);
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void translationFault(const Fault &fault);
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PacketPtr buildPacket(RequestPtr req, bool read);
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void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
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RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read);
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bool handleReadPacket(PacketPtr pkt);
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// This function always implicitly uses dcache_pkt.
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bool handleWritePacket();
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/**
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* A TimingCPUPort overrides the default behaviour of the
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* recvTiming and recvRetry and implements events for the
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* scheduling of handling of incoming packets in the following
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* cycle.
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*/
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class TimingCPUPort : public MasterPort
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{
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public:
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TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
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: MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
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{ }
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protected:
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/**
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* Snooping a coherence request, do nothing.
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*/
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virtual void recvTimingSnoopReq(PacketPtr pkt) {}
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TimingSimpleCPU* cpu;
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struct TickEvent : public Event
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{
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PacketPtr pkt;
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TimingSimpleCPU *cpu;
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TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
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const char *description() const { return "Timing CPU tick"; }
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void schedule(PacketPtr _pkt, Tick t);
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};
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EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent;
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};
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class IcachePort : public TimingCPUPort
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{
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public:
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IcachePort(TimingSimpleCPU *_cpu)
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: TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
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tickEvent(_cpu)
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{ }
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protected:
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual void recvReqRetry();
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struct ITickEvent : public TickEvent
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{
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ITickEvent(TimingSimpleCPU *_cpu)
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: TickEvent(_cpu) {}
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void process();
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const char *description() const { return "Timing CPU icache tick"; }
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};
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ITickEvent tickEvent;
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};
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class DcachePort : public TimingCPUPort
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{
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public:
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DcachePort(TimingSimpleCPU *_cpu)
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: TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
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tickEvent(_cpu)
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{
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cacheBlockMask = ~(cpu->cacheLineSize() - 1);
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}
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Addr cacheBlockMask;
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protected:
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/** Snoop a coherence request, we need to check if this causes
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* a wakeup event on a cpu that is monitoring an address
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*/
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virtual void recvTimingSnoopReq(PacketPtr pkt);
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virtual void recvFunctionalSnoop(PacketPtr pkt);
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual void recvReqRetry();
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virtual bool isSnooping() const {
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return true;
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}
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struct DTickEvent : public TickEvent
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{
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DTickEvent(TimingSimpleCPU *_cpu)
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: TickEvent(_cpu) {}
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void process();
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const char *description() const { return "Timing CPU dcache tick"; }
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};
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DTickEvent tickEvent;
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};
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void updateCycleCounts();
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IcachePort icachePort;
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DcachePort dcachePort;
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PacketPtr ifetch_pkt;
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PacketPtr dcache_pkt;
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Cycles previousCycle;
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protected:
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/** Return a reference to the data port. */
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MasterPort &getDataPort() override { return dcachePort; }
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/** Return a reference to the instruction port. */
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MasterPort &getInstPort() override { return icachePort; }
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public:
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DrainState drain() override;
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void drainResume() override;
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void switchOut() override;
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void takeOverFrom(BaseCPU *oldCPU) override;
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void verifyMemoryMode() const override;
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void activateContext(ThreadID thread_num) override;
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void suspendContext(ThreadID thread_num) override;
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Fault readMem(Addr addr, uint8_t *data, unsigned size,
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unsigned flags) override;
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Fault writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res) override;
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void fetch();
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void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
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void completeIfetch(PacketPtr );
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void completeDataAccess(PacketPtr pkt);
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void advanceInst(const Fault &fault);
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/** This function is used by the page table walker to determine if it could
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* translate the a pending request or if the underlying request has been
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* squashed. This always returns false for the simple timing CPU as it never
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* executes any instructions speculatively.
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* @ return Is the current instruction squashed?
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*/
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bool isSquashed() const { return false; }
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/**
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* Print state of address in memory system via PrintReq (for
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* debugging).
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*/
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void printAddr(Addr a);
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/**
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* Finish a DTB translation.
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* @param state The DTB translation state.
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*/
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void finishTranslation(WholeTranslationState *state);
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private:
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typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
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FetchEvent fetchEvent;
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struct IprEvent : Event {
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Packet *pkt;
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TimingSimpleCPU *cpu;
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IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
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virtual void process();
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virtual const char *description() const;
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};
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/**
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* Check if a system is in a drained state.
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*
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* We need to drain if:
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* <ul>
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* <li>We are in the middle of a microcode sequence as some CPUs
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* (e.g., HW accelerated CPUs) can't be started in the middle
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* of a gem5 microcode sequence.
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*
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* <li>Stay at PC is true.
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*
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* <li>A fetch event is scheduled. Normally this would never be the
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* case with microPC() == 0, but right after a context is
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* activated it can happen.
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* </ul>
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*/
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bool isDrained() {
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SimpleExecContext& t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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return thread->microPC() == 0 && !t_info.stayAtPC &&
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!fetchEvent.scheduled();
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}
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/**
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* Try to complete a drain request.
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*
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* @returns true if the CPU is drained, false otherwise.
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*/
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bool tryCompleteDrain();
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};
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#endif // __CPU_SIMPLE_TIMING_HH__
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