2ac04c11ac
This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables).
736 lines
22 KiB
C++
736 lines
22 KiB
C++
/*
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* Copyright (c) 2011-2013 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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* Rick Strong
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*/
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#ifndef __CPU_O3_CPU_HH__
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#define __CPU_O3_CPU_HH__
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#include <iostream>
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#include <list>
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#include <queue>
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#include <set>
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#include <vector>
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#include "arch/types.hh"
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#include "base/statistics.hh"
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#include "config/the_isa.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/cpu_policy.hh"
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#include "cpu/o3/scoreboard.hh"
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#include "cpu/o3/thread_state.hh"
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#include "cpu/activity.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/timebuf.hh"
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//#include "cpu/o3/thread_context.hh"
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#include "params/DerivO3CPU.hh"
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#include "sim/process.hh"
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template <class>
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class Checker;
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class ThreadContext;
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template <class>
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class O3ThreadContext;
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class Checkpoint;
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class MemObject;
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class Process;
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struct BaseCPUParams;
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class BaseO3CPU : public BaseCPU
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{
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//Stuff that's pretty ISA independent will go here.
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public:
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BaseO3CPU(BaseCPUParams *params);
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void regStats();
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};
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/**
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* FullO3CPU class, has each of the stages (fetch through commit)
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* within it, as well as all of the time buffers between stages. The
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* tick() function for the CPU is defined here.
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*/
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template <class Impl>
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class FullO3CPU : public BaseO3CPU
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{
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public:
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// Typedefs from the Impl here.
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typedef typename Impl::CPUPol CPUPolicy;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::O3CPU O3CPU;
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typedef O3ThreadState<Impl> ImplState;
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typedef O3ThreadState<Impl> Thread;
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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friend class O3ThreadContext<Impl>;
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public:
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enum Status {
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Running,
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Idle,
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Halted,
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Blocked,
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SwitchedOut
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};
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TheISA::TLB * itb;
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TheISA::TLB * dtb;
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/** Overall CPU status. */
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Status _status;
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private:
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/**
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* IcachePort class for instruction fetch.
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*/
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class IcachePort : public MasterPort
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{
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protected:
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/** Pointer to fetch. */
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DefaultFetch<Impl> *fetch;
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public:
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/** Default constructor. */
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IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
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: MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
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{ }
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protected:
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/** Timing version of receive. Handles setting fetch to the
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* proper status to start fetching. */
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual void recvTimingSnoopReq(PacketPtr pkt) { }
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/** Handles doing a retry of a failed fetch. */
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virtual void recvReqRetry();
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};
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/**
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* DcachePort class for the load/store queue.
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*/
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class DcachePort : public MasterPort
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{
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protected:
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/** Pointer to LSQ. */
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LSQ<Impl> *lsq;
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FullO3CPU<Impl> *cpu;
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public:
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/** Default constructor. */
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DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
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: MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
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cpu(_cpu)
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{ }
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protected:
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/** Timing version of receive. Handles writing back and
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* completing the load or store that has returned from
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* memory. */
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual void recvTimingSnoopReq(PacketPtr pkt);
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virtual void recvFunctionalSnoop(PacketPtr pkt)
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{
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// @todo: Is there a need for potential invalidation here?
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}
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/** Handles doing a retry of the previous send. */
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virtual void recvReqRetry();
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/**
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* As this CPU requires snooping to maintain the load store queue
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* change the behaviour from the base CPU port.
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*
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* @return true since we have to snoop
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*/
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virtual bool isSnooping() const { return true; }
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};
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class TickEvent : public Event
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{
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private:
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/** Pointer to the CPU. */
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FullO3CPU<Impl> *cpu;
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public:
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/** Constructs a tick event. */
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TickEvent(FullO3CPU<Impl> *c);
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/** Processes a tick event, calling tick() on the CPU. */
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void process();
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/** Returns the description of the tick event. */
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const char *description() const;
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};
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/** The tick event used for scheduling CPU ticks. */
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TickEvent tickEvent;
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/** Schedule tick event, regardless of its current state. */
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void scheduleTickEvent(Cycles delay)
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{
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if (tickEvent.squashed())
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reschedule(tickEvent, clockEdge(delay));
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else if (!tickEvent.scheduled())
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schedule(tickEvent, clockEdge(delay));
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}
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/** Unschedule tick event, regardless of its current state. */
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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/**
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* Check if the pipeline has drained and signal drain done.
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*
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* This method checks if a drain has been requested and if the CPU
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* has drained successfully (i.e., there are no instructions in
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* the pipeline). If the CPU has drained, it deschedules the tick
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* event and signals the drain manager.
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*
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* @return False if a drain hasn't been requested or the CPU
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* hasn't drained, true otherwise.
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*/
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bool tryDrain();
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/**
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* Perform sanity checks after a drain.
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*
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* This method is called from drain() when it has determined that
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* the CPU is fully drained when gem5 is compiled with the NDEBUG
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* macro undefined. The intention of this method is to do more
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* extensive tests than the isDrained() method to weed out any
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* draining bugs.
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*/
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void drainSanityCheck() const;
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/** Check if a system is in a drained state. */
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bool isDrained() const;
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public:
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/** Constructs a CPU with the given parameters. */
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FullO3CPU(DerivO3CPUParams *params);
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/** Destructor. */
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~FullO3CPU();
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/** Registers statistics. */
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void regStats() override;
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ProbePointArg<PacketPtr> *ppInstAccessComplete;
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ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
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/** Register probe points. */
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void regProbePoints() override;
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void demapPage(Addr vaddr, uint64_t asn)
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{
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this->itb->demapPage(vaddr, asn);
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this->dtb->demapPage(vaddr, asn);
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}
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void demapInstPage(Addr vaddr, uint64_t asn)
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{
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this->itb->demapPage(vaddr, asn);
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}
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void demapDataPage(Addr vaddr, uint64_t asn)
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{
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this->dtb->demapPage(vaddr, asn);
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}
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/** Ticks CPU, calling tick() on each stage, and checking the overall
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* activity to see if the CPU should deschedule itself.
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*/
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void tick();
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/** Initialize the CPU */
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void init() override;
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void startup() override;
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/** Returns the Number of Active Threads in the CPU */
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int numActiveThreads()
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{ return activeThreads.size(); }
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/** Add Thread to Active Threads List */
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void activateThread(ThreadID tid);
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/** Remove Thread from Active Threads List */
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void deactivateThread(ThreadID tid);
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/** Setup CPU to insert a thread's context */
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void insertThread(ThreadID tid);
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/** Remove all of a thread's context from CPU */
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void removeThread(ThreadID tid);
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/** Count the Total Instructions Committed in the CPU. */
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Counter totalInsts() const override;
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/** Count the Total Ops (including micro ops) committed in the CPU. */
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Counter totalOps() const override;
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/** Add Thread to Active Threads List. */
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void activateContext(ThreadID tid) override;
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/** Remove Thread from Active Threads List */
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void suspendContext(ThreadID tid) override;
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/** Remove Thread from Active Threads List &&
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* Remove Thread Context from CPU.
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*/
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void haltContext(ThreadID tid) override;
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/** Update The Order In Which We Process Threads. */
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void updateThreadPriority();
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/** Is the CPU draining? */
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bool isDraining() const { return drainState() == DrainState::Draining; }
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void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
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void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
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public:
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/** Executes a syscall.
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* @todo: Determine if this needs to be virtual.
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*/
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void syscall(int64_t callnum, ThreadID tid);
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/** Starts draining the CPU's pipeline of all instructions in
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* order to stop all memory accesses. */
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DrainState drain() override;
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/** Resumes execution after a drain. */
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void drainResume() override;
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/**
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* Commit has reached a safe point to drain a thread.
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*
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* Commit calls this method to inform the pipeline that it has
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* reached a point where it is not executed microcode and is about
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* to squash uncommitted instructions to fully drain the pipeline.
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*/
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void commitDrained(ThreadID tid);
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/** Switches out this CPU. */
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void switchOut() override;
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/** Takes over from another CPU. */
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void takeOverFrom(BaseCPU *oldCPU) override;
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void verifyMemoryMode() const override;
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/** Get the current instruction sequence number, and increment it. */
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InstSeqNum getAndIncrementInstSeq()
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{ return globalSeqNum++; }
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/** Traps to handle given fault. */
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void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
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/** HW return from error interrupt. */
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Fault hwrei(ThreadID tid);
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bool simPalCheck(int palFunc, ThreadID tid);
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/** Returns the Fault for any valid interrupt. */
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Fault getInterrupts();
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/** Processes any an interrupt fault. */
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void processInterrupts(const Fault &interrupt);
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/** Halts the CPU. */
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void halt() { panic("Halt not implemented!\n"); }
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/** Register accessors. Index refers to the physical register index. */
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/** Reads a miscellaneous register. */
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TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
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/** Reads a misc. register, including any side effects the read
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* might have as defined by the architecture.
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*/
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TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
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/** Sets a miscellaneous register. */
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void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
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ThreadID tid);
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/** Sets a misc. register, including any side effects the write
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* might have as defined by the architecture.
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*/
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void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
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ThreadID tid);
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uint64_t readIntReg(int reg_idx);
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TheISA::FloatReg readFloatReg(int reg_idx);
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TheISA::FloatRegBits readFloatRegBits(int reg_idx);
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TheISA::CCReg readCCReg(int reg_idx);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatReg(int reg_idx, TheISA::FloatReg val);
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void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
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void setCCReg(int reg_idx, TheISA::CCReg val);
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uint64_t readArchIntReg(int reg_idx, ThreadID tid);
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float readArchFloatReg(int reg_idx, ThreadID tid);
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uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
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TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
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/** Architectural register accessors. Looks up in the commit
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* rename table to obtain the true physical index of the
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* architected register first, then accesses that physical
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* register.
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*/
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void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
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void setArchFloatReg(int reg_idx, float val, ThreadID tid);
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void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
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void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
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/** Sets the commit PC state of a specific thread. */
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void pcState(const TheISA::PCState &newPCState, ThreadID tid);
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/** Reads the commit PC state of a specific thread. */
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TheISA::PCState pcState(ThreadID tid);
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/** Reads the commit PC of a specific thread. */
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Addr instAddr(ThreadID tid);
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/** Reads the commit micro PC of a specific thread. */
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MicroPC microPC(ThreadID tid);
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/** Reads the next PC of a specific thread. */
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Addr nextInstAddr(ThreadID tid);
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/** Initiates a squash of all in-flight instructions for a given
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* thread. The source of the squash is an external update of
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* state through the TC.
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*/
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void squashFromTC(ThreadID tid);
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/** Function to add instruction onto the head of the list of the
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* instructions. Used when new instructions are fetched.
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*/
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ListIt addInst(DynInstPtr &inst);
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/** Function to tell the CPU that an instruction has completed. */
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void instDone(ThreadID tid, DynInstPtr &inst);
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/** Remove an instruction from the front end of the list. There's
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* no restriction on location of the instruction.
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*/
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void removeFrontInst(DynInstPtr &inst);
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/** Remove all instructions that are not currently in the ROB.
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* There's also an option to not squash delay slot instructions.*/
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void removeInstsNotInROB(ThreadID tid);
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/** Remove all instructions younger than the given sequence number. */
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void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
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/** Removes the instruction pointed to by the iterator. */
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inline void squashInstIt(const ListIt &instIt, ThreadID tid);
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/** Cleans up all instructions on the remove list. */
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void cleanUpRemovedInsts();
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|
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/** Debug function to print all instructions on the list. */
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void dumpInsts();
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public:
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|
#ifndef NDEBUG
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/** Count of total number of dynamic instructions in flight. */
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int instcount;
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#endif
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|
|
/** List of all the instructions in flight. */
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std::list<DynInstPtr> instList;
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|
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/** List of all the instructions that will be removed at the end of this
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* cycle.
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*/
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std::queue<ListIt> removeList;
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|
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#ifdef DEBUG
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/** Debug structure to keep track of the sequence numbers still in
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* flight.
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*/
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std::set<InstSeqNum> snList;
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#endif
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|
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/** Records if instructions need to be removed this cycle due to
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* being retired or squashed.
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*/
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|
bool removeInstsThisCycle;
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|
|
protected:
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/** The fetch stage. */
|
|
typename CPUPolicy::Fetch fetch;
|
|
|
|
/** The decode stage. */
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|
typename CPUPolicy::Decode decode;
|
|
|
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/** The dispatch stage. */
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|
typename CPUPolicy::Rename rename;
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|
|
|
/** The issue/execute/writeback stages. */
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|
typename CPUPolicy::IEW iew;
|
|
|
|
/** The commit stage. */
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|
typename CPUPolicy::Commit commit;
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|
|
/** The register file. */
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PhysRegFile regFile;
|
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|
|
/** The free list. */
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|
typename CPUPolicy::FreeList freeList;
|
|
|
|
/** The rename map. */
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|
typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
|
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|
|
/** The commit rename map. */
|
|
typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
|
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/** The re-order buffer. */
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typename CPUPolicy::ROB rob;
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/** Active Threads List */
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std::list<ThreadID> activeThreads;
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/** Integer Register Scoreboard */
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Scoreboard scoreboard;
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std::vector<TheISA::ISA *> isa;
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/** Instruction port. Note that it has to appear after the fetch stage. */
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IcachePort icachePort;
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/** Data port. Note that it has to appear after the iew stages */
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DcachePort dcachePort;
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public:
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/** Enum to give each stage a specific index, so when calling
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* activateStage() or deactivateStage(), they can specify which stage
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* is being activated/deactivated.
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*/
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enum StageIdx {
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FetchIdx,
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DecodeIdx,
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RenameIdx,
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|
IEWIdx,
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CommitIdx,
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NumStages };
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/** Typedefs from the Impl to get the structs that each of the
|
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* time buffers should use.
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*/
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typedef typename CPUPolicy::TimeStruct TimeStruct;
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typedef typename CPUPolicy::FetchStruct FetchStruct;
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typedef typename CPUPolicy::DecodeStruct DecodeStruct;
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typedef typename CPUPolicy::RenameStruct RenameStruct;
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typedef typename CPUPolicy::IEWStruct IEWStruct;
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|
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/** The main time buffer to do backwards communication. */
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TimeBuffer<TimeStruct> timeBuffer;
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|
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/** The fetch stage's instruction queue. */
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TimeBuffer<FetchStruct> fetchQueue;
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|
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/** The decode stage's instruction queue. */
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TimeBuffer<DecodeStruct> decodeQueue;
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|
|
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/** The rename stage's instruction queue. */
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TimeBuffer<RenameStruct> renameQueue;
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|
|
|
/** The IEW stage's instruction queue. */
|
|
TimeBuffer<IEWStruct> iewQueue;
|
|
|
|
private:
|
|
/** The activity recorder; used to tell if the CPU has any
|
|
* activity remaining or if it can go to idle and deschedule
|
|
* itself.
|
|
*/
|
|
ActivityRecorder activityRec;
|
|
|
|
public:
|
|
/** Records that there was time buffer activity this cycle. */
|
|
void activityThisCycle() { activityRec.activity(); }
|
|
|
|
/** Changes a stage's status to active within the activity recorder. */
|
|
void activateStage(const StageIdx idx)
|
|
{ activityRec.activateStage(idx); }
|
|
|
|
/** Changes a stage's status to inactive within the activity recorder. */
|
|
void deactivateStage(const StageIdx idx)
|
|
{ activityRec.deactivateStage(idx); }
|
|
|
|
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
|
|
void wakeCPU();
|
|
|
|
virtual void wakeup(ThreadID tid) override;
|
|
|
|
/** Gets a free thread id. Use if thread ids change across system. */
|
|
ThreadID getFreeTid();
|
|
|
|
public:
|
|
/** Returns a pointer to a thread context. */
|
|
ThreadContext *
|
|
tcBase(ThreadID tid)
|
|
{
|
|
return thread[tid]->getTC();
|
|
}
|
|
|
|
/** The global sequence number counter. */
|
|
InstSeqNum globalSeqNum;//[Impl::MaxThreads];
|
|
|
|
/** Pointer to the checker, which can dynamically verify
|
|
* instruction results at run time. This can be set to NULL if it
|
|
* is not being used.
|
|
*/
|
|
Checker<Impl> *checker;
|
|
|
|
/** Pointer to the system. */
|
|
System *system;
|
|
|
|
/** Pointers to all of the threads in the CPU. */
|
|
std::vector<Thread *> thread;
|
|
|
|
/** Threads Scheduled to Enter CPU */
|
|
std::list<int> cpuWaitList;
|
|
|
|
/** The cycle that the CPU was last running, used for statistics. */
|
|
Cycles lastRunningCycle;
|
|
|
|
/** The cycle that the CPU was last activated by a new thread*/
|
|
Tick lastActivatedCycle;
|
|
|
|
/** Mapping for system thread id to cpu id */
|
|
std::map<ThreadID, unsigned> threadMap;
|
|
|
|
/** Available thread ids in the cpu*/
|
|
std::vector<ThreadID> tids;
|
|
|
|
/** CPU read function, forwards read to LSQ. */
|
|
Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
|
|
uint8_t *data, int load_idx)
|
|
{
|
|
return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
|
|
data, load_idx);
|
|
}
|
|
|
|
/** CPU write function, forwards write to LSQ. */
|
|
Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
|
|
uint8_t *data, int store_idx)
|
|
{
|
|
return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
|
|
data, store_idx);
|
|
}
|
|
|
|
/** Used by the fetch unit to get a hold of the instruction port. */
|
|
MasterPort &getInstPort() override { return icachePort; }
|
|
|
|
/** Get the dcache port (used to find block size for translations). */
|
|
MasterPort &getDataPort() override { return dcachePort; }
|
|
|
|
/** Stat for total number of times the CPU is descheduled. */
|
|
Stats::Scalar timesIdled;
|
|
/** Stat for total number of cycles the CPU spends descheduled. */
|
|
Stats::Scalar idleCycles;
|
|
/** Stat for total number of cycles the CPU spends descheduled due to a
|
|
* quiesce operation or waiting for an interrupt. */
|
|
Stats::Scalar quiesceCycles;
|
|
/** Stat for the number of committed instructions per thread. */
|
|
Stats::Vector committedInsts;
|
|
/** Stat for the number of committed ops (including micro ops) per thread. */
|
|
Stats::Vector committedOps;
|
|
/** Stat for the CPI per thread. */
|
|
Stats::Formula cpi;
|
|
/** Stat for the total CPI. */
|
|
Stats::Formula totalCpi;
|
|
/** Stat for the IPC per thread. */
|
|
Stats::Formula ipc;
|
|
/** Stat for the total IPC. */
|
|
Stats::Formula totalIpc;
|
|
|
|
//number of integer register file accesses
|
|
Stats::Scalar intRegfileReads;
|
|
Stats::Scalar intRegfileWrites;
|
|
//number of float register file accesses
|
|
Stats::Scalar fpRegfileReads;
|
|
Stats::Scalar fpRegfileWrites;
|
|
//number of CC register file accesses
|
|
Stats::Scalar ccRegfileReads;
|
|
Stats::Scalar ccRegfileWrites;
|
|
//number of misc
|
|
Stats::Scalar miscRegfileReads;
|
|
Stats::Scalar miscRegfileWrites;
|
|
};
|
|
|
|
#endif // __CPU_O3_CPU_HH__
|