496c48d9b2
console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file
575 lines
16 KiB
C
575 lines
16 KiB
C
#ifndef EV5_DEFS_INCLUDED
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#define EV5_DEFS_INCLUDED 1
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// adapted from the version emailed to lance..pb Nov/95
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// ********************************************************************************************************************************
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// Created 25-JUL-1995 14:21:23 by VAX SDL V3.2-12 Source: 21-JUL-1995 11:03:08 EV5$:[EV5.DVT.SUP]EV5_DEFS.SDL;24
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// ********************************************************************************************************************************
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// .MACRO $EV5DEF,..EQU=<=>,..COL=<:>
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// EV5$K_REVISION'..equ'34
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// In the definitions below, registers are annotated with one of the following
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// symbols:
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//
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// RW - The register may be read and written
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// RO - The register may only be read
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// WO - The register may only be written
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//
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// For RO and WO registers, all bits and fields within the register are also
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// read-only or write-only. For RW registers, each bit or field within
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// the register is annotated with one of the following:
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//
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// RW - The bit/field may be read and written
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// RO - The bit/field may be read; writes are ignored
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// WO - The bit/field may be written; reads return an UNPREDICTABLE result.
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// WZ - The bit/field may be written; reads return a 0
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// WC - The bit/field may be read; writes cause state to clear
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// RC - The bit/field may be read, which also causes state to clear; writes are ignored
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// Architecturally-defined (SRM) registers for EVMS
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#define pt0 320
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#define pt1 321
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#define pt2 322
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#define pt3 323
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#define pt4 324
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#define pt5 325
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#define pt6 326
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#define pt7 327
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#define pt8 328
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#define pt9 329
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#define pt10 330
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#define pt11 331
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#define pt12 332
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#define pt13 333
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#define pt14 334
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#define pt15 335
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#define pt16 336
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#define pt17 337
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#define pt18 338
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#define pt19 339
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#define pt20 340
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#define pt21 341
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#define pt22 342
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#define pt23 343
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#define cbox_ipr_offset 16777200
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#define sc_ctl 168
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#define sc_stat 232
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#define sc_addr 392
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#define sc_addr_nm 392
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#define sc_addr_fhm 392
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#define bc_ctl 296
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#define bc_config 456
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#define ei_stat 360
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#define ei_addr 328
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#define fill_syn 104
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#define bc_tag_addr 264
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#define ld_lock 488
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#define aster 266
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#define astrr 265
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#define exc_addr 267
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#define exc_sum 268
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#define exc_mask 269
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#define hwint_clr 277
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#define ic_flush_ctl 281
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#define icperr_stat 282
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#define ic_perr_stat 282
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#define ic_row_map 283
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#define icsr 280
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#define ifault_va_form 274
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#define intid 273
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#define ipl 272
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#define isr 256
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#define itb_is 263
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#define itb_asn 259
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#define itb_ia 261
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#define itb_iap 262
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#define itb_pte 258
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#define itb_pte_temp 260
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#define itb_tag 257
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#define ivptbr 275
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#define pal_base 270
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#define pmctr 284
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// this is not the register ps .. pb #define ps 271
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#define sirr 264
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#define sl_txmit 278
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#define sl_rcv 279
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#define alt_mode 524
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#define cc 525
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#define cc_ctl 526
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#define dc_flush 528
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#define dcperr_stat 530
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#define dc_test_ctl 531
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#define dc_test_tag 532
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#define dc_test_tag_temp 533
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#define dtb_asn 512
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#define dtb_cm 513
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#define dtb_ia 522
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#define dtb_iap 521
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#define dtb_is 523
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#define dtb_pte 515
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#define dtb_pte_temp 516
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#define dtb_tag 514
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#define mcsr 527
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#define dc_mode 534
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#define maf_mode 535
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#define mm_stat 517
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#define mvptbr 520
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#define va 518
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#define va_form 519
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#define ev5_srm__ps 0
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#define ev5_srm__pc 0
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#define ev5_srm__asten 0
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#define ev5_srm__astsr 0
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#define ev5_srm__ipir 0
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#define ev5_srm__ipl 0
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#define ev5_srm__mces 0
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#define ev5_srm__pcbb 0
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#define ev5_srm__prbr 0
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#define ev5_srm__ptbr 0
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#define ev5_srm__scbb 0
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#define ev5_srm__sirr 0
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#define ev5_srm__sisr 0
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#define ev5_srm__tbchk 0
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#define ev5_srm__tb1a 0
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#define ev5_srm__tb1ap 0
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#define ev5_srm__tb1ad 0
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#define ev5_srm__tb1ai 0
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#define ev5_srm__tbis 0
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#define ev5_srm__ksp 0
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#define ev5_srm__esp 0
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#define ev5_srm__ssp 0
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#define ev5_srm__usp 0
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#define ev5_srm__vptb 0
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#define ev5_srm__whami 0
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#define ev5_srm__cc 0
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#define ev5_srm__unq 0
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// processor-specific iprs.
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#define ev5__sc_ctl 168
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#define ev5__sc_stat 232
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#define ev5__sc_addr 392
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#define ev5__bc_ctl 296
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#define ev5__bc_config 456
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#define bc_config_k_size_1mb 1
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#define bc_config_k_size_2mb 2
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#define bc_config_k_size_4mb 3
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#define bc_config_k_size_8mb 4
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#define bc_config_k_size_16mb 5
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#define bc_config_k_size_32mb 6
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#define bc_config_k_size_64mb 7
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#define ev5__ei_stat 360
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#define ev5__ei_addr 328
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#define ev5__fill_syn 104
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#define ev5__bc_tag_addr 264
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#define ev5__aster 266
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#define ev5__astrr 265
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#define ev5__exc_addr 267
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#define exc_addr_v_pa 2
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#define exc_addr_s_pa 62
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#define ev5__exc_sum 268
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#define ev5__exc_mask 269
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#define ev5__hwint_clr 277
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#define ev5__ic_flush_ctl 281
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#define ev5__icperr_stat 282
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#define ev5__ic_perr_stat 282
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#define ev5__ic_row_map 283
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#define ev5__icsr 280
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#define ev5__ifault_va_form 274
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#define ev5__ifault_va_form_nt 274
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#define ifault_va_form_nt_v_vptb 30
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#define ifault_va_form_nt_s_vptb 34
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#define ev5__intid 273
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#define ev5__ipl 272
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#define ev5__itb_is 263
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#define ev5__itb_asn 259
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#define ev5__itb_ia 261
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#define ev5__itb_iap 262
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#define ev5__itb_pte 258
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#define ev5__itb_pte_temp 260
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#define ev5__itb_tag 257
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#define ev5__ivptbr 275
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#define ivptbr_v_vptb 30
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#define ivptbr_s_vptb 34
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#define ev5__pal_base 270
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#define ev5__pmctr 284
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#define ev5__ps 271
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#define ev5__isr 256
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#define ev5__sirr 264
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#define ev5__sl_txmit 278
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#define ev5__sl_rcv 279
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#define ev5__alt_mode 524
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#define ev5__cc 525
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#define ev5__cc_ctl 526
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#define ev5__dc_flush 528
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#define ev5__dcperr_stat 530
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#define ev5__dc_test_ctl 531
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#define ev5__dc_test_tag 532
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#define ev5__dc_test_tag_temp 533
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#define ev5__dtb_asn 512
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#define ev5__dtb_cm 513
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#define ev5__dtb_ia 522
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#define ev5__dtb_iap 521
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#define ev5__dtb_is 523
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#define ev5__dtb_pte 515
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#define ev5__dtb_pte_temp 516
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#define ev5__dtb_tag 514
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#define ev5__mcsr 527
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#define ev5__dc_mode 534
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#define ev5__maf_mode 535
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#define ev5__mm_stat 517
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#define ev5__mvptbr 520
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#define ev5__va 518
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#define ev5__va_form 519
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#define ev5__va_form_nt 519
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#define va_form_nt_s_va 19
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#define va_form_nt_v_vptb 30
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#define va_form_nt_s_vptb 34
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#define ev5s_ev5_def 10
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#define ev5_def 0
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// cbox registers.
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#define sc_ctl_v_sc_fhit 0
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#define sc_ctl_v_sc_flush 1
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#define sc_ctl_s_sc_tag_stat 6
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#define sc_ctl_v_sc_tag_stat 2
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#define sc_ctl_s_sc_fb_dp 4
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#define sc_ctl_v_sc_fb_dp 8
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#define sc_ctl_v_sc_blk_size 12
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#define sc_ctl_s_sc_set_en 3
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#define sc_ctl_v_sc_set_en 13
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#define sc_ctl_s_sc_soft_repair 3
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#define sc_ctl_v_sc_soft_repair 16
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#define sc_stat_s_sc_tperr 3
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#define sc_stat_v_sc_tperr 0
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#define sc_stat_s_sc_dperr 8
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#define sc_stat_v_sc_dperr 3
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#define sc_stat_s_cbox_cmd 5
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#define sc_stat_v_cbox_cmd 11
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#define sc_stat_v_sc_scnd_err 16
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#define sc_addr_fhm_v_sc_tag_parity 4
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#define sc_addr_fhm_s_tag_stat_sb0 3
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#define sc_addr_fhm_v_tag_stat_sb0 5
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#define sc_addr_fhm_s_tag_stat_sb1 3
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#define sc_addr_fhm_v_tag_stat_sb1 8
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#define sc_addr_fhm_s_ow_mod0 2
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#define sc_addr_fhm_v_ow_mod0 11
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#define sc_addr_fhm_s_ow_mod1 2
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#define sc_addr_fhm_v_ow_mod1 13
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#define sc_addr_fhm_s_tag_lo 17
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#define sc_addr_fhm_v_tag_lo 15
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#define sc_addr_fhm_s_tag_hi 7
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#define sc_addr_fhm_v_tag_hi 32
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#define bc_ctl_v_bc_enabled 0
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#define bc_ctl_v_alloc_cyc 1
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#define bc_ctl_v_ei_opt_cmd 2
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#define bc_ctl_v_ei_opt_cmd_mb 3
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#define bc_ctl_v_corr_fill_dat 4
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#define bc_ctl_v_vtm_first 5
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#define bc_ctl_v_ei_ecc_or_parity 6
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#define bc_ctl_v_bc_fhit 7
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#define bc_ctl_s_bc_tag_stat 5
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#define bc_ctl_v_bc_tag_stat 8
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#define bc_ctl_s_bc_bad_dat 2
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#define bc_ctl_v_bc_bad_dat 13
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#define bc_ctl_v_ei_dis_err 15
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#define bc_ctl_v_tl_pipe_latch 16
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#define bc_ctl_s_bc_wave_pipe 2
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#define bc_ctl_v_bc_wave_pipe 17
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#define bc_ctl_s_pm_mux_sel 6
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#define bc_ctl_v_pm_mux_sel 19
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#define bc_ctl_v_dbg_mux_sel 25
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#define bc_ctl_v_dis_baf_byp 26
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#define bc_ctl_v_dis_sc_vic_buf 27
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#define bc_ctl_v_dis_sys_addr_par 28
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#define bc_ctl_v_read_dirty_cln_shr 29
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#define bc_ctl_v_write_read_bubble 30
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#define bc_ctl_v_bc_wave_pipe_2 31
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#define bc_ctl_v_auto_dack 32
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#define bc_ctl_v_dis_byte_word 33
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#define bc_ctl_v_stclk_delay 34
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#define bc_ctl_v_write_under_miss 35
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#define bc_config_s_bc_size 3
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#define bc_config_v_bc_size 0
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#define bc_config_s_bc_rd_spd 4
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#define bc_config_v_bc_rd_spd 4
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#define bc_config_s_bc_wr_spd 4
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#define bc_config_v_bc_wr_spd 8
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#define bc_config_s_bc_rd_wr_spc 3
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#define bc_config_v_bc_rd_wr_spc 12
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#define bc_config_s_fill_we_offset 3
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#define bc_config_v_fill_we_offset 16
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#define bc_config_s_bc_we_ctl 9
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#define bc_config_v_bc_we_ctl 20
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// cbox registers, continued
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#define ei_stat_s_sys_id 4
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#define ei_stat_v_sys_id 24
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#define ei_stat_v_bc_tperr 28
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#define ei_stat_v_bc_tc_perr 29
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#define ei_stat_v_ei_es 30
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#define ei_stat_v_cor_ecc_err 31
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#define ei_stat_v_unc_ecc_err 32
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#define ei_stat_v_ei_par_err 33
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#define ei_stat_v_fil_ird 34
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#define ei_stat_v_seo_hrd_err 35
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//
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#define bc_tag_addr_v_hit 12
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#define bc_tag_addr_v_tagctl_p 13
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#define bc_tag_addr_v_tagctl_d 14
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#define bc_tag_addr_v_tagctl_s 15
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#define bc_tag_addr_v_tagctl_v 16
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#define bc_tag_addr_v_tag_p 17
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#define bc_tag_addr_s_bc_tag 19
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#define bc_tag_addr_v_bc_tag 20
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// ibox and icache registers.
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#define aster_v_kar 0
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#define aster_v_ear 1
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#define aster_v_sar 2
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#define aster_v_uar 3
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#define astrr_v_kar 0
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#define astrr_v_ear 1
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#define astrr_v_sar 2
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#define astrr_v_uar 3
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#define exc_addr_v_pal 0
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#define exc_sum_v_swc 10
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#define exc_sum_v_inv 11
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#define exc_sum_v_dze 12
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#define exc_sum_v_fov 13
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#define exc_sum_v_unf 14
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#define exc_sum_v_ine 15
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#define exc_sum_v_iov 16
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#define hwint_clr_v_pc0c 27
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#define hwint_clr_v_pc1c 28
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#define hwint_clr_v_pc2c 29
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#define hwint_clr_v_crdc 32
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#define hwint_clr_v_slc 33
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// ibox and icache registers, continued
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#define icperr_stat_v_dpe 11
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#define icperr_stat_v_tpe 12
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#define icperr_stat_v_tmr 13
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#define ic_perr_stat_v_dpe 11
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#define ic_perr_stat_v_tpe 12
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#define ic_perr_stat_v_tmr 13
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#define icsr_v_pma 8
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#define icsr_v_pmp 9
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#define icsr_v_byt 17
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#define icsr_v_fmp 18
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#define icsr_v_im0 20
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#define icsr_v_im1 21
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#define icsr_v_im2 22
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#define icsr_v_im3 23
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#define icsr_v_tmm 24
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#define icsr_v_tmd 25
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#define icsr_v_fpe 26
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#define icsr_v_hwe 27
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#define icsr_s_spe 2
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#define icsr_v_spe 28
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#define icsr_v_sde 30
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#define icsr_v_crde 32
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#define icsr_v_sle 33
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#define icsr_v_fms 34
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#define icsr_v_fbt 35
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#define icsr_v_fbd 36
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#define icsr_v_dbs 37
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#define icsr_v_ista 38
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#define icsr_v_tst 39
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#define ifault_va_form_s_va 30
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#define ifault_va_form_v_va 3
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#define ifault_va_form_s_vptb 31
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#define ifault_va_form_v_vptb 33
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#define ifault_va_form_nt_s_va 19
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#define ifault_va_form_nt_v_va 3
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#define intid_s_intid 5
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#define intid_v_intid 0
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// ibox and icache registers, continued
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#define ipl_s_ipl 5
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#define ipl_v_ipl 0
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#define itb_is_s_va 30
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#define itb_is_v_va 13
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#define itb_asn_s_asn 7
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#define itb_asn_v_asn 4
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#define itb_pte_v_asm 4
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#define itb_pte_s_gh 2
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#define itb_pte_v_gh 5
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#define itb_pte_v_kre 8
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#define itb_pte_v_ere 9
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#define itb_pte_v_sre 10
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#define itb_pte_v_ure 11
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#define itb_pte_s_pfn 27
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#define itb_pte_v_pfn 32
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#define itb_pte_temp_v_asm 13
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#define itb_pte_temp_v_kre 18
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#define itb_pte_temp_v_ere 19
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#define itb_pte_temp_v_sre 20
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#define itb_pte_temp_v_ure 21
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#define itb_pte_temp_s_gh 3
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#define itb_pte_temp_v_gh 29
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#define itb_pte_temp_s_pfn 27
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#define itb_pte_temp_v_pfn 32
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// ibox and icache registers, continued
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#define itb_tag_s_va 30
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#define itb_tag_v_va 13
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#define pal_base_s_pal_base 26
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#define pal_base_v_pal_base 14
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#define pmctr_s_sel2 4
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#define pmctr_v_sel2 0
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#define pmctr_s_sel1 4
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#define pmctr_v_sel1 4
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#define pmctr_v_killk 8
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#define pmctr_v_killp 9
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#define pmctr_s_ctl2 2
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#define pmctr_v_ctl2 10
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#define pmctr_s_ctl1 2
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#define pmctr_v_ctl1 12
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#define pmctr_s_ctl0 2
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#define pmctr_v_ctl0 14
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#define pmctr_s_ctr2 14
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#define pmctr_v_ctr2 16
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#define pmctr_v_killu 30
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#define pmctr_v_sel0 31
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#define pmctr_s_ctr1 16
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#define pmctr_v_ctr1 32
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#define pmctr_s_ctr0 16
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#define pmctr_v_ctr0 48
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#define ps_v_cm0 3
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#define ps_v_cm1 4
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#define isr_s_astrr 4
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#define isr_v_astrr 0
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#define isr_s_sisr 15
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#define isr_v_sisr 4
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#define isr_v_atr 19
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#define isr_v_i20 20
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#define isr_v_i21 21
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#define isr_v_i22 22
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#define isr_v_i23 23
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#define isr_v_pc0 27
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#define isr_v_pc1 28
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#define isr_v_pc2 29
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#define isr_v_pfl 30
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#define isr_v_mck 31
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#define isr_v_crd 32
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#define isr_v_sli 33
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#define isr_v_hlt 34
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#define sirr_s_sirr 15
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#define sirr_v_sirr 4
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// ibox and icache registers, continued
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#define sl_txmit_v_tmt 7
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#define sl_rcv_v_rcv 6
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// mbox and dcache registers.
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#define alt_mode_v_am0 3
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#define alt_mode_v_am1 4
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#define cc_ctl_v_cc_ena 32
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#define dcperr_stat_v_seo 0
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#define dcperr_stat_v_lock 1
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#define dcperr_stat_v_dp0 2
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#define dcperr_stat_v_dp1 3
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#define dcperr_stat_v_tp0 4
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#define dcperr_stat_v_tp1 5
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// the following two registers are used exclusively for test and diagnostics.
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// they should not be referenced in normal operation.
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#define dc_test_ctl_v_bank0 0
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#define dc_test_ctl_v_bank1 1
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#define dc_test_ctl_v_fill_0 2
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#define dc_test_ctl_s_index 10
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#define dc_test_ctl_v_index 3
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#define dc_test_ctl_s_fill_1 19
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#define dc_test_ctl_v_fill_1 13
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#define dc_test_ctl_s_fill_2 32
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#define dc_test_ctl_v_fill_2 32
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// mbox and dcache registers, continued.
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#define dc_test_tag_v_tag_par 2
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#define dc_test_tag_v_ow0 11
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#define dc_test_tag_v_ow1 12
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#define dc_test_tag_s_tag 26
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#define dc_test_tag_v_tag 13
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#define dc_test_tag_temp_v_tag_par 2
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#define dc_test_tag_temp_v_d0p0 3
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#define dc_test_tag_temp_v_d0p1 4
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#define dc_test_tag_temp_v_d1p0 5
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#define dc_test_tag_temp_v_d1p1 6
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#define dc_test_tag_temp_v_ow0 11
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#define dc_test_tag_temp_v_ow1 12
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#define dc_test_tag_temp_s_tag 26
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#define dc_test_tag_temp_v_tag 13
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#define dtb_asn_s_asn 7
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#define dtb_asn_v_asn 57
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#define dtb_cm_v_cm0 3
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#define dtb_cm_v_cm1 4
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#define dtbis_s_va0 30
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#define dtbis_v_va0 13
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#define dtb_pte_v_for 1
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#define dtb_pte_v_fow 2
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#define dtb_pte_v_asm 4
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#define dtb_pte_s_gh 2
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#define dtb_pte_v_gh 5
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#define dtb_pte_v_kre 8
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#define dtb_pte_v_ere 9
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#define dtb_pte_v_sre 10
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#define dtb_pte_v_ure 11
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#define dtb_pte_v_kwe 12
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#define dtb_pte_v_ewe 13
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#define dtb_pte_v_swe 14
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#define dtb_pte_v_uwe 15
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#define dtb_pte_s_pfn 27
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#define dtb_pte_v_pfn 32
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// mbox and dcache registers, continued.
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#define dtb_pte_temp_v_for 0
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|
#define dtb_pte_temp_v_fow 1
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#define dtb_pte_temp_v_kre 2
|
|
#define dtb_pte_temp_v_ere 3
|
|
#define dtb_pte_temp_v_sre 4
|
|
#define dtb_pte_temp_v_ure 5
|
|
#define dtb_pte_temp_v_kwe 6
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|
#define dtb_pte_temp_v_ewe 7
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|
#define dtb_pte_temp_v_swe 8
|
|
#define dtb_pte_temp_v_uwe 9
|
|
#define dtb_pte_temp_v_asm 10
|
|
#define dtb_pte_temp_s_fill_0 2
|
|
#define dtb_pte_temp_v_fill_0 11
|
|
#define dtb_pte_temp_s_pfn 27
|
|
#define dtb_pte_temp_v_pfn 13
|
|
#define dtb_tag_s_va 30
|
|
#define dtb_tag_v_va 13
|
|
// most mcsr bits are used for testability and diagnostics only.
|
|
// for normal operation, they will be supported in the following configuration:
|
|
// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0,
|
|
// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0
|
|
#define mcsr_v_big_endian 0
|
|
#define mcsr_v_sp0 1
|
|
#define mcsr_v_sp1 2
|
|
#define mcsr_v_mbox_sel 3
|
|
#define mcsr_v_e_big_endian 4
|
|
#define mcsr_v_dbg_packet_sel 5
|
|
#define dc_mode_v_dc_ena 0
|
|
#define dc_mode_v_dc_fhit 1
|
|
#define dc_mode_v_dc_bad_parity 2
|
|
#define dc_mode_v_dc_perr_dis 3
|
|
#define dc_mode_v_dc_doa 4
|
|
#define maf_mode_v_maf_nomerge 0
|
|
#define maf_mode_v_wb_flush_always 1
|
|
#define maf_mode_v_wb_nomerge 2
|
|
#define maf_mode_v_io_nomerge 3
|
|
#define maf_mode_v_wb_cnt_disable 4
|
|
#define maf_mode_v_maf_arb_disable 5
|
|
#define maf_mode_v_dread_pending 6
|
|
#define maf_mode_v_wb_pending 7
|
|
// mbox and dcache registers, continued.
|
|
#define mm_stat_v_wr 0
|
|
#define mm_stat_v_acv 1
|
|
#define mm_stat_v_for 2
|
|
#define mm_stat_v_fow 3
|
|
#define mm_stat_v_dtb_miss 4
|
|
#define mm_stat_v_bad_va 5
|
|
#define mm_stat_s_ra 5
|
|
#define mm_stat_v_ra 6
|
|
#define mm_stat_s_opcode 6
|
|
#define mm_stat_v_opcode 11
|
|
#define mvptbr_s_vptb 31
|
|
#define mvptbr_v_vptb 33
|
|
#define va_form_s_va 30
|
|
#define va_form_v_va 3
|
|
#define va_form_s_vptb 31
|
|
#define va_form_v_vptb 33
|
|
#define va_form_nt_s_va 19
|
|
#define va_form_nt_v_va 3
|
|
//.endm
|
|
|
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#endif
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