2974dc7a37
Swig wrappers for native objects currently share the _m5.internal name space with Python code. This is undesirable if we ever want to switch from Swig to some other framework for native binding (e.g., PyBind11 or Boost::Python). This changeset moves all of such wrappers to the _m5 namespace, which is now reserved for native code. Change-Id: I2d2bc12dbc05b57b7c5a75f072e08124413d77f3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
372 lines
13 KiB
Python
372 lines
13 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005 The Regents of The University of Michigan
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# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Steve Reinhardt
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import atexit
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import os
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import sys
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# import the SWIG-wrapped main C++ functions
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import _m5.drain
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import _m5.core
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from _m5.stats import updateEvents as updateStatEvents
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import stats
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import SimObject
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import ticks
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import objects
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from m5.util.dot_writer import do_dot, do_dvfs_dot
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from util import fatal
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from util import attrdict
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# define a MaxTick parameter, unsigned 64 bit
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MaxTick = 2**64 - 1
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_memory_modes = {
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"atomic" : objects.params.atomic,
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"timing" : objects.params.timing,
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"atomic_noncaching" : objects.params.atomic_noncaching,
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}
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_drain_manager = _m5.drain.DrainManager.instance()
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# The final hook to generate .ini files. Called from the user script
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# once the config is built.
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def instantiate(ckpt_dir=None):
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from m5 import options
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root = objects.Root.getInstance()
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if not root:
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fatal("Need to instantiate Root() before calling instantiate()")
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# we need to fix the global frequency
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ticks.fixGlobalFrequency()
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# Make sure SimObject-valued params are in the configuration
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# hierarchy so we catch them with future descendants() walks
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for obj in root.descendants(): obj.adoptOrphanParams()
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# Unproxy in sorted order for determinism
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for obj in root.descendants(): obj.unproxyParams()
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if options.dump_config:
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ini_file = file(os.path.join(options.outdir, options.dump_config), 'w')
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# Print ini sections in sorted order for easier diffing
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for obj in sorted(root.descendants(), key=lambda o: o.path()):
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obj.print_ini(ini_file)
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ini_file.close()
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if options.json_config:
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try:
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import json
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json_file = file(os.path.join(options.outdir, options.json_config), 'w')
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d = root.get_config_as_dict()
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json.dump(d, json_file, indent=4)
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json_file.close()
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except ImportError:
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pass
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do_dot(root, options.outdir, options.dot_config)
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# Initialize the global statistics
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stats.initSimStats()
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# Create the C++ sim objects and connect ports
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for obj in root.descendants(): obj.createCCObject()
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for obj in root.descendants(): obj.connectPorts()
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# Do a second pass to finish initializing the sim objects
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for obj in root.descendants(): obj.init()
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# Do a third pass to initialize statistics
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for obj in root.descendants(): obj.regStats()
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# Do a fourth pass to initialize probe points
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for obj in root.descendants(): obj.regProbePoints()
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# Do a fifth pass to connect probe listeners
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for obj in root.descendants(): obj.regProbeListeners()
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# We want to generate the DVFS diagram for the system. This can only be
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# done once all of the CPP objects have been created and initialised so
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# that we are able to figure out which object belongs to which domain.
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if options.dot_dvfs_config:
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do_dvfs_dot(root, options.outdir, options.dot_dvfs_config)
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# We're done registering statistics. Enable the stats package now.
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stats.enable()
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# Restore checkpoint (if any)
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if ckpt_dir:
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_drain_manager.preCheckpointRestore()
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ckpt = _m5.core.getCheckpoint(ckpt_dir)
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_m5.core.unserializeGlobals(ckpt);
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for obj in root.descendants(): obj.loadState(ckpt)
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else:
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for obj in root.descendants(): obj.initState()
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# Check to see if any of the stat events are in the past after resuming from
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# a checkpoint, If so, this call will shift them to be at a valid time.
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updateStatEvents()
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need_startup = True
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def simulate(*args, **kwargs):
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global need_startup
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if need_startup:
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root = objects.Root.getInstance()
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for obj in root.descendants(): obj.startup()
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need_startup = False
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# Python exit handlers happen in reverse order.
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# We want to dump stats last.
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atexit.register(stats.dump)
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# register our C++ exit callback function with Python
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atexit.register(_m5.core.doExitCleanup)
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# Reset to put the stats in a consistent state.
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stats.reset()
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if _drain_manager.isDrained():
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_drain_manager.resume()
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return _m5.event.simulate(*args, **kwargs)
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def drain():
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"""Drain the simulator in preparation of a checkpoint or memory mode
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switch.
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This operation is a no-op if the simulator is already in the
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Drained state.
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"""
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# Try to drain all objects. Draining might not be completed unless
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# all objects return that they are drained on the first call. This
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# is because as objects drain they may cause other objects to no
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# longer be drained.
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def _drain():
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# Try to drain the system. The drain is successful if all
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# objects are done without simulation. We need to simulate
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# more if not.
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if _drain_manager.tryDrain():
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return True
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# WARNING: if a valid exit event occurs while draining, it
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# will not get returned to the user script
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exit_event = _m5.event.simulate()
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while exit_event.getCause() != 'Finished drain':
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exit_event = simulate()
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return False
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# Don't try to drain a system that is already drained
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is_drained = _drain_manager.isDrained()
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while not is_drained:
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is_drained = _drain()
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assert _drain_manager.isDrained(), "Drain state inconsistent"
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def memWriteback(root):
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for obj in root.descendants():
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obj.memWriteback()
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def memInvalidate(root):
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for obj in root.descendants():
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obj.memInvalidate()
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def checkpoint(dir):
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root = objects.Root.getInstance()
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if not isinstance(root, objects.Root):
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raise TypeError, "Checkpoint must be called on a root object."
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drain()
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memWriteback(root)
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print "Writing checkpoint"
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_m5.core.serializeAll(dir)
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def _changeMemoryMode(system, mode):
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if not isinstance(system, (objects.Root, objects.System)):
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raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
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(type(system), objects.Root, objects.System)
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if system.getMemoryMode() != mode:
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system.setMemoryMode(mode)
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else:
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print "System already in target mode. Memory mode unchanged."
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def switchCpus(system, cpuList, verbose=True):
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"""Switch CPUs in a system.
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Note: This method may switch the memory mode of the system if that
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is required by the CPUs. It may also flush all caches in the
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system.
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Arguments:
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system -- Simulated system.
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cpuList -- (old_cpu, new_cpu) tuples
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"""
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if verbose:
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print "switching cpus"
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if not isinstance(cpuList, list):
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raise RuntimeError, "Must pass a list to this function"
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for item in cpuList:
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if not isinstance(item, tuple) or len(item) != 2:
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raise RuntimeError, "List must have tuples of (oldCPU,newCPU)"
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old_cpus = [old_cpu for old_cpu, new_cpu in cpuList]
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new_cpus = [new_cpu for old_cpu, new_cpu in cpuList]
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old_cpu_set = set(old_cpus)
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memory_mode_name = new_cpus[0].memory_mode()
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for old_cpu, new_cpu in cpuList:
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if not isinstance(old_cpu, objects.BaseCPU):
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raise TypeError, "%s is not of type BaseCPU" % old_cpu
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if not isinstance(new_cpu, objects.BaseCPU):
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raise TypeError, "%s is not of type BaseCPU" % new_cpu
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if new_cpu in old_cpu_set:
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raise RuntimeError, \
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"New CPU (%s) is in the list of old CPUs." % (old_cpu,)
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if not new_cpu.switchedOut():
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raise RuntimeError, \
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"New CPU (%s) is already active." % (new_cpu,)
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if not new_cpu.support_take_over():
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raise RuntimeError, \
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"New CPU (%s) does not support CPU handover." % (old_cpu,)
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if new_cpu.memory_mode() != memory_mode_name:
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raise RuntimeError, \
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"%s and %s require different memory modes." % (new_cpu,
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new_cpus[0])
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if old_cpu.switchedOut():
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raise RuntimeError, \
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"Old CPU (%s) is inactive." % (new_cpu,)
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if not old_cpu.support_take_over():
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raise RuntimeError, \
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"Old CPU (%s) does not support CPU handover." % (old_cpu,)
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try:
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memory_mode = _memory_modes[memory_mode_name]
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except KeyError:
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raise RuntimeError, "Invalid memory mode (%s)" % memory_mode_name
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drain()
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# Now all of the CPUs are ready to be switched out
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for old_cpu, new_cpu in cpuList:
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old_cpu.switchOut()
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# Change the memory mode if required. We check if this is needed
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# to avoid printing a warning if no switch was performed.
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if system.getMemoryMode() != memory_mode:
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# Flush the memory system if we are switching to a memory mode
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# that disables caches. This typically happens when switching to a
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# hardware virtualized CPU.
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if memory_mode == objects.params.atomic_noncaching:
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memWriteback(system)
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memInvalidate(system)
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_changeMemoryMode(system, memory_mode)
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for old_cpu, new_cpu in cpuList:
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new_cpu.takeOverFrom(old_cpu)
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def notifyFork(root):
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for obj in root.descendants():
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obj.notifyFork()
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fork_count = 0
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def fork(simout="%(parent)s.f%(fork_seq)i"):
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"""Fork the simulator.
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This function forks the simulator. After forking the simulator,
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the child process gets its output files redirected to a new output
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directory. The default name of the output directory is the same as
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the parent with the suffix ".fN" added where N is the fork
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sequence number. The name of the output directory can be
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overridden using the simout keyword argument.
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Output file formatting dictionary:
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parent -- Path to the parent process's output directory.
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fork_seq -- Fork sequence number.
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pid -- PID of the child process.
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Keyword Arguments:
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simout -- New simulation output directory.
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Return Value:
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pid of the child process or 0 if running in the child.
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"""
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from m5 import options
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global fork_count
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if not _m5.core.listenersDisabled():
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raise RuntimeError, "Can not fork a simulator with listeners enabled"
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drain()
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try:
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pid = os.fork()
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except OSError, e:
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raise e
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if pid == 0:
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# In child, notify objects of the fork
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root = objects.Root.getInstance()
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notifyFork(root)
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# Setup a new output directory
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parent = options.outdir
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options.outdir = simout % {
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"parent" : parent,
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"fork_seq" : fork_count,
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"pid" : os.getpid(),
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}
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_m5.core.setOutputDir(options.outdir)
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else:
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fork_count += 1
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return pid
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from _m5.core import disableAllListeners, listenersDisabled
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from _m5.core import curTick
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