1162 lines
66 KiB
C++
1162 lines
66 KiB
C++
/*****************************************************************************
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* McPAT
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2012 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include <algorithm>
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#include <cassert>
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#include <cmath>
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#include <cstring>
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#include <iostream>
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#include "XML_Parse.h"
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#include "arbiter.h"
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#include "array.h"
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#include "basic_circuit.h"
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#include "const.h"
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#include "io.h"
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#include "logic.h"
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#include "parameter.h"
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#include "sharedcache.h"
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SharedCache::SharedCache(ParseXML* XML_interface, int ithCache_, InputParameter* interface_ip_, enum cache_level cacheL_)
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:XML(XML_interface),
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ithCache(ithCache_),
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interface_ip(*interface_ip_),
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cacheL(cacheL_),
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dir_overhead(0)
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{
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int idx;
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int tag, data;
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bool is_default, debug;
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enum Device_ty device_t;
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enum Core_type core_t;
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double size, line, assoc, banks;
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if (cacheL==L2 && XML->sys.Private_L2)
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{
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device_t=Core_device;
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core_t = (enum Core_type)XML->sys.core[ithCache].machine_type;
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}
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else
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{
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device_t=LLC_device;
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core_t = Inorder;
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}
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debug = false;
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is_default=true;//indication for default setup
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if (XML->sys.Embedded)
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{
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interface_ip.wt =Global_30;
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interface_ip.wire_is_mat_type = 0;
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interface_ip.wire_os_mat_type = 1;
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}
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else
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{
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interface_ip.wt =Global;
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interface_ip.wire_is_mat_type = 2;
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interface_ip.wire_os_mat_type = 2;
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}
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set_cache_param();
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//All lower level cache are physically indexed and tagged.
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size = cachep.capacity;
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line = cachep.blockW;
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assoc = cachep.assoc;
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banks = cachep.nbanks;
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if ((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory))
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{
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assoc = 0;
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
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interface_ip.num_search_ports = 1;
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}
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else
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{
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idx = debug?9:int(ceil(log2(size/line/assoc)));
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tag = debug?51:XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
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interface_ip.num_search_ports = 0;
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if (cachep.dir_ty==SBT)
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{
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dir_overhead = ceil(XML->sys.number_of_cores/8.0)*8/(cachep.blockW*8);
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line = cachep.blockW*(1+ dir_overhead) ;
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size = cachep.capacity*(1+ dir_overhead);
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}
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}
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// if (XML->sys.first_level_dir==2)
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// tag += int(XML->sys.domain_size + 5);
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.cache_sz = (int)size;
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interface_ip.line_sz = (int)line;
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interface_ip.assoc = (int)assoc;
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interface_ip.nbanks = (int)banks;
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interface_ip.out_w = interface_ip.line_sz*8/2;
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interface_ip.access_mode = 1;
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interface_ip.throughput = cachep.throughput;
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interface_ip.latency = cachep.latency;
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interface_ip.is_cache = true;
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interface_ip.pure_ram = false;
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interface_ip.pure_cam = false;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;//lower level cache usually has one port.
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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// interface_ip.force_cache_config =true;
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// interface_ip.ndwl = 4;
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// interface_ip.ndbl = 8;
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// interface_ip.nspd = 1;
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// interface_ip.ndcm =1 ;
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// interface_ip.ndsam1 =1;
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// interface_ip.ndsam2 =1;
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unicache.caches = new ArrayST(&interface_ip, cachep.name + "cache", device_t, true, core_t);
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unicache.area.set_area(unicache.area.get_area()+ unicache.caches->local_result.area);
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area.set_area(area.get_area()+ unicache.caches->local_result.area);
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interface_ip.force_cache_config =false;
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if (!((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory)))
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{
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
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data = (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + unicache.caches->l_ip.line_sz;
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0));
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interface_ip.cache_sz = cachep.missb_size*interface_ip.line_sz;
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interface_ip.assoc = 0;
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interface_ip.is_cache = true;
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interface_ip.pure_ram = false;
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interface_ip.pure_cam = false;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8/2;
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interface_ip.access_mode = 0;
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interface_ip.throughput = cachep.throughput;//means cycle time
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interface_ip.latency = cachep.latency;//means access time
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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interface_ip.num_search_ports = 1;
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unicache.missb = new ArrayST(&interface_ip, cachep.name + "MissB", device_t, true, core_t);
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unicache.area.set_area(unicache.area.get_area()+ unicache.missb->local_result.area);
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area.set_area(area.get_area()+ unicache.missb->local_result.area);
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//fill buffer
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
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data = unicache.caches->l_ip.line_sz;
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
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interface_ip.cache_sz = data*cachep.fu_size ;
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interface_ip.assoc = 0;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8/2;
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interface_ip.access_mode = 0;
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interface_ip.throughput = cachep.throughput;
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interface_ip.latency = cachep.latency;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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unicache.ifb = new ArrayST(&interface_ip, cachep.name + "FillB", device_t, true, core_t);
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unicache.area.set_area(unicache.area.get_area()+ unicache.ifb->local_result.area);
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area.set_area(area.get_area()+ unicache.ifb->local_result.area);
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//prefetch buffer
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries to decide wthether to merge.
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data = unicache.caches->l_ip.line_sz;//separate queue to prevent from cache polution.
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
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interface_ip.cache_sz = cachep.prefetchb_size*interface_ip.line_sz;
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interface_ip.assoc = 0;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8/2;
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interface_ip.access_mode = 0;
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interface_ip.throughput = cachep.throughput;
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interface_ip.latency = cachep.latency;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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unicache.prefetchb = new ArrayST(&interface_ip, cachep.name + "PrefetchB", device_t, true, core_t);
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unicache.area.set_area(unicache.area.get_area()+ unicache.prefetchb->local_result.area);
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area.set_area(area.get_area()+ unicache.prefetchb->local_result.area);
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//WBB
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
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data = unicache.caches->l_ip.line_sz;
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = data;
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interface_ip.cache_sz = cachep.wbb_size*interface_ip.line_sz;
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interface_ip.assoc = 0;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8/2;
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interface_ip.access_mode = 0;
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interface_ip.throughput = cachep.throughput;
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interface_ip.latency = cachep.latency;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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unicache.wbb = new ArrayST(&interface_ip, cachep.name + "WBB", device_t, true, core_t);
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unicache.area.set_area(unicache.area.get_area()+ unicache.wbb->local_result.area);
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area.set_area(area.get_area()+ unicache.wbb->local_result.area);
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}
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// //pipeline
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// interface_ip.pipeline_stages = int(ceil(llCache.caches.local_result.access_time/llCache.caches.local_result.cycle_time));
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// interface_ip.per_stage_vector = llCache.caches.l_ip.out_w + llCache.caches.l_ip.tag_w ;
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// pipeLogicCache.init_pipeline(is_default, &interface_ip);
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// pipeLogicCache.compute_pipeline();
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/*
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if (!((XML->sys.number_of_dir_levels==1 && XML->sys.first_level_dir ==1)
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||(XML->sys.number_of_dir_levels==1 && XML->sys.first_level_dir ==2)))//not single level IC and DIC
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{
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//directory Now assuming one directory per bank, TODO:should change it later
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size = XML->sys.L2directory.L2Dir_config[0];
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line = XML->sys.L2directory.L2Dir_config[1];
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assoc = XML->sys.L2directory.L2Dir_config[2];
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banks = XML->sys.L2directory.L2Dir_config[3];
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tag = debug?51:XML->sys.physical_address_width + EXTRA_TAG_BITS;//TODO: a little bit over estimate
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interface_ip.specific_tag = 0;
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interface_ip.tag_w = tag;
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interface_ip.cache_sz = XML->sys.L2directory.L2Dir_config[0];
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interface_ip.line_sz = XML->sys.L2directory.L2Dir_config[1];
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interface_ip.assoc = XML->sys.L2directory.L2Dir_config[2];
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interface_ip.nbanks = XML->sys.L2directory.L2Dir_config[3];
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interface_ip.out_w = interface_ip.line_sz*8;
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interface_ip.access_mode = 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5];
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interface_ip.throughput = XML->sys.L2directory.L2Dir_config[4]/clockRate;
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interface_ip.latency = XML->sys.L2directory.L2Dir_config[5]/clockRate;
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interface_ip.is_cache = true;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;//lower level cache usually has one port.
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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strcpy(directory.caches.name,"L2 Directory");
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directory.caches.init_cache(&interface_ip);
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directory.caches.optimize_array();
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directory.area += directory.caches.local_result.area;
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//output_data_csv(directory.caches.local_result);
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///cout<<"area="<<area<<endl;
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//miss buffer Each MSHR contains enough state to handle one or more accesses of any type to a single memory line.
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//Due to the generality of the MSHR mechanism, the amount of state involved is non-trivial,
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//including the address, pointers to the cache entry and destination register, written data, and various other pieces of state.
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
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data = (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + directory.caches.l_ip.line_sz;
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0));
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interface_ip.cache_sz = XML->sys.L2[ithCache].buffer_sizes[0]*interface_ip.line_sz;
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interface_ip.assoc = 0;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8;
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interface_ip.access_mode = 0;
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interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;//means cycle time
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interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;//means access time
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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strcpy(directory.missb.name,"directoryMissB");
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directory.missb.init_cache(&interface_ip);
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directory.missb.optimize_array();
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directory.area += directory.missb.local_result.area;
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//output_data_csv(directory.missb.local_result);
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///cout<<"area="<<area<<endl;
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//fill buffer
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
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data = directory.caches.l_ip.line_sz;
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
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interface_ip.cache_sz = data*XML->sys.L2[ithCache].buffer_sizes[1];
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interface_ip.assoc = 0;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8;
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interface_ip.access_mode = 0;
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interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
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interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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strcpy(directory.ifb.name,"directoryFillB");
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directory.ifb.init_cache(&interface_ip);
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directory.ifb.optimize_array();
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directory.area += directory.ifb.local_result.area;
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//output_data_csv(directory.ifb.local_result);
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///cout<<"area="<<area<<endl;
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//prefetch buffer
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tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries to decide wthether to merge.
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data = directory.caches.l_ip.line_sz;//separate queue to prevent from cache polution.
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interface_ip.specific_tag = 1;
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interface_ip.tag_w = tag;
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interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
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interface_ip.cache_sz = XML->sys.L2[ithCache].buffer_sizes[2]*interface_ip.line_sz;
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interface_ip.assoc = 0;
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interface_ip.nbanks = 1;
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interface_ip.out_w = interface_ip.line_sz*8;
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interface_ip.access_mode = 0;
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interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
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interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;
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interface_ip.obj_func_dyn_energy = 0;
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interface_ip.obj_func_dyn_power = 0;
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interface_ip.obj_func_leak_power = 0;
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interface_ip.obj_func_cycle_t = 1;
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interface_ip.num_rw_ports = 1;
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interface_ip.num_rd_ports = 0;
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interface_ip.num_wr_ports = 0;
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interface_ip.num_se_rd_ports = 0;
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strcpy(directory.prefetchb.name,"directoryPrefetchB");
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directory.prefetchb.init_cache(&interface_ip);
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directory.prefetchb.optimize_array();
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directory.area += directory.prefetchb.local_result.area;
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//output_data_csv(directory.prefetchb.local_result);
|
|
///cout<<"area="<<area<<endl;
|
|
|
|
//WBB
|
|
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
|
|
data = directory.caches.l_ip.line_sz;
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.line_sz = data;
|
|
interface_ip.cache_sz = XML->sys.L2[ithCache].buffer_sizes[3]*interface_ip.line_sz;
|
|
interface_ip.assoc = 0;
|
|
interface_ip.nbanks = 1;
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;
|
|
interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
|
|
interface_ip.latency = XML->sys.L2[ithCache].L2_config[4]/clockRate;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
strcpy(directory.wbb.name,"directoryWBB");
|
|
directory.wbb.init_cache(&interface_ip);
|
|
directory.wbb.optimize_array();
|
|
directory.area += directory.wbb.local_result.area;
|
|
}
|
|
|
|
if (XML->sys.number_of_dir_levels ==2 && XML->sys.first_level_dir==0)
|
|
{
|
|
//first level directory
|
|
size = XML->sys.L2directory.L2Dir_config[0]*XML->sys.domain_size/128;
|
|
line = int(ceil(XML->sys.domain_size/8.0));
|
|
assoc = XML->sys.L2directory.L2Dir_config[2];
|
|
banks = XML->sys.L2directory.L2Dir_config[3];
|
|
tag = debug?51:XML->sys.physical_address_width + EXTRA_TAG_BITS;//TODO: a little bit over estimate
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.cache_sz = XML->sys.L2directory.L2Dir_config[0];
|
|
interface_ip.line_sz = XML->sys.L2directory.L2Dir_config[1];
|
|
interface_ip.assoc = XML->sys.L2directory.L2Dir_config[2];
|
|
interface_ip.nbanks = XML->sys.L2directory.L2Dir_config[3];
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;//debug?0:XML->sys.core[ithCore].icache.icache_config[5];
|
|
interface_ip.throughput = XML->sys.L2directory.L2Dir_config[4]/clockRate;
|
|
interface_ip.latency = XML->sys.L2directory.L2Dir_config[5]/clockRate;
|
|
interface_ip.is_cache = true;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;//lower level cache usually has one port.
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
|
|
strcpy(directory1.caches.name,"first level Directory");
|
|
directory1.caches.init_cache(&interface_ip);
|
|
directory1.caches.optimize_array();
|
|
directory1.area += directory1.caches.local_result.area;
|
|
//output_data_csv(directory.caches.local_result);
|
|
///cout<<"area="<<area<<endl;
|
|
|
|
//miss buffer Each MSHR contains enough state to handle one or more accesses of any type to a single memory line.
|
|
//Due to the generality of the MSHR mechanism, the amount of state involved is non-trivial,
|
|
//including the address, pointers to the cache entry and destination register, written data, and various other pieces of state.
|
|
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
|
|
data = (XML->sys.physical_address_width) + int(ceil(log2(size/line))) + directory1.caches.l_ip.line_sz;
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.line_sz = int(ceil(data/8.0));//int(ceil(pow(2.0,ceil(log2(data)))/8.0));
|
|
interface_ip.cache_sz = XML->sys.L2[ithCache].buffer_sizes[0]*interface_ip.line_sz;
|
|
interface_ip.assoc = 0;
|
|
interface_ip.nbanks = 1;
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;
|
|
interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;//means cycle time
|
|
interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;//means access time
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
strcpy(directory1.missb.name,"directory1MissB");
|
|
directory1.missb.init_cache(&interface_ip);
|
|
directory1.missb.optimize_array();
|
|
directory1.area += directory1.missb.local_result.area;
|
|
//output_data_csv(directory.missb.local_result);
|
|
///cout<<"area="<<area<<endl;
|
|
|
|
//fill buffer
|
|
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
|
|
data = directory1.caches.l_ip.line_sz;
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
|
|
interface_ip.cache_sz = data*XML->sys.L2[ithCache].buffer_sizes[1];
|
|
interface_ip.assoc = 0;
|
|
interface_ip.nbanks = 1;
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;
|
|
interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
|
|
interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
strcpy(directory1.ifb.name,"directory1FillB");
|
|
directory1.ifb.init_cache(&interface_ip);
|
|
directory1.ifb.optimize_array();
|
|
directory1.area += directory1.ifb.local_result.area;
|
|
//output_data_csv(directory.ifb.local_result);
|
|
///cout<<"area="<<area<<endl;
|
|
|
|
//prefetch buffer
|
|
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;//check with previous entries to decide wthether to merge.
|
|
data = directory1.caches.l_ip.line_sz;//separate queue to prevent from cache polution.
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.line_sz = data;//int(pow(2.0,ceil(log2(data))));
|
|
interface_ip.cache_sz = XML->sys.L2[ithCache].buffer_sizes[2]*interface_ip.line_sz;
|
|
interface_ip.assoc = 0;
|
|
interface_ip.nbanks = 1;
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;
|
|
interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
|
|
interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
strcpy(directory1.prefetchb.name,"directory1PrefetchB");
|
|
directory1.prefetchb.init_cache(&interface_ip);
|
|
directory1.prefetchb.optimize_array();
|
|
directory1.area += directory1.prefetchb.local_result.area;
|
|
//output_data_csv(directory.prefetchb.local_result);
|
|
///cout<<"area="<<area<<endl;
|
|
|
|
//WBB
|
|
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
|
|
data = directory1.caches.l_ip.line_sz;
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.line_sz = data;
|
|
interface_ip.cache_sz = XML->sys.L2[ithCache].buffer_sizes[3]*interface_ip.line_sz;
|
|
interface_ip.assoc = 0;
|
|
interface_ip.nbanks = 1;
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;
|
|
interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
|
|
interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
strcpy(directory1.wbb.name,"directoryWBB");
|
|
directory1.wbb.init_cache(&interface_ip);
|
|
directory1.wbb.optimize_array();
|
|
directory1.area += directory1.wbb.local_result.area;
|
|
}
|
|
|
|
if (XML->sys.first_level_dir==1)//IC
|
|
{
|
|
tag = XML->sys.physical_address_width + EXTRA_TAG_BITS;
|
|
data = int(ceil(XML->sys.domain_size/8.0));
|
|
interface_ip.specific_tag = 1;
|
|
interface_ip.tag_w = tag;
|
|
interface_ip.line_sz = data;
|
|
interface_ip.cache_sz = XML->sys.domain_size*data*XML->sys.L2[ithCache].L2_config[0]/XML->sys.L2[ithCache].L2_config[1];
|
|
interface_ip.assoc = 0;
|
|
interface_ip.nbanks = 1024;
|
|
interface_ip.out_w = interface_ip.line_sz*8;
|
|
interface_ip.access_mode = 0;
|
|
interface_ip.throughput = XML->sys.L2[ithCache].L2_config[4]/clockRate;
|
|
interface_ip.latency = XML->sys.L2[ithCache].L2_config[5]/clockRate;
|
|
interface_ip.obj_func_dyn_energy = 0;
|
|
interface_ip.obj_func_dyn_power = 0;
|
|
interface_ip.obj_func_leak_power = 0;
|
|
interface_ip.obj_func_cycle_t = 1;
|
|
interface_ip.num_rw_ports = 1;
|
|
interface_ip.num_rd_ports = 0;
|
|
interface_ip.num_wr_ports = 0;
|
|
interface_ip.num_se_rd_ports = 0;
|
|
strcpy(inv_dir.caches.name,"inv_dir");
|
|
inv_dir.caches.init_cache(&interface_ip);
|
|
inv_dir.caches.optimize_array();
|
|
inv_dir.area = inv_dir.caches.local_result.area;
|
|
|
|
}
|
|
*/
|
|
// //pipeline
|
|
// interface_ip.pipeline_stages = int(ceil(directory.caches.local_result.access_time/directory.caches.local_result.cycle_time));
|
|
// interface_ip.per_stage_vector = directory.caches.l_ip.out_w + directory.caches.l_ip.tag_w ;
|
|
// pipeLogicDirectory.init_pipeline(is_default, &interface_ip);
|
|
// pipeLogicDirectory.compute_pipeline();
|
|
//
|
|
// //clock power
|
|
// clockNetwork.init_wire_external(is_default, &interface_ip);
|
|
// clockNetwork.clk_area =area*1.1;//10% of placement overhead. rule of thumb
|
|
// clockNetwork.end_wiring_level =5;//toplevel metal
|
|
// clockNetwork.start_wiring_level =5;//toplevel metal
|
|
// clockNetwork.num_regs = pipeLogicCache.tot_stage_vector + pipeLogicDirectory.tot_stage_vector;
|
|
// clockNetwork.optimize_wire();
|
|
|
|
}
|
|
|
|
|
|
void SharedCache::computeEnergy(bool is_tdp)
|
|
{
|
|
double homenode_data_access = (cachep.dir_ty==SBT)? 0.9:1.0;
|
|
if (is_tdp)
|
|
{
|
|
if (!((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory)))
|
|
{
|
|
//init stats for Peak
|
|
unicache.caches->stats_t.readAc.access = .67*unicache.caches->l_ip.num_rw_ports*cachep.duty_cycle*homenode_data_access;
|
|
unicache.caches->stats_t.readAc.miss = 0;
|
|
unicache.caches->stats_t.readAc.hit = unicache.caches->stats_t.readAc.access - unicache.caches->stats_t.readAc.miss;
|
|
unicache.caches->stats_t.writeAc.access = .33*unicache.caches->l_ip.num_rw_ports*cachep.duty_cycle*homenode_data_access;
|
|
unicache.caches->stats_t.writeAc.miss = 0;
|
|
unicache.caches->stats_t.writeAc.hit = unicache.caches->stats_t.writeAc.access - unicache.caches->stats_t.writeAc.miss;
|
|
unicache.caches->tdp_stats = unicache.caches->stats_t;
|
|
|
|
if (cachep.dir_ty==SBT)
|
|
{
|
|
homenode_stats_t.readAc.access = .67*unicache.caches->l_ip.num_rw_ports*cachep.dir_duty_cycle*(1-homenode_data_access);
|
|
homenode_stats_t.readAc.miss = 0;
|
|
homenode_stats_t.readAc.hit = homenode_stats_t.readAc.access - homenode_stats_t.readAc.miss;
|
|
homenode_stats_t.writeAc.access = .67*unicache.caches->l_ip.num_rw_ports*cachep.dir_duty_cycle*(1-homenode_data_access);
|
|
homenode_stats_t.writeAc.miss = 0;
|
|
homenode_stats_t.writeAc.hit = homenode_stats_t.writeAc.access - homenode_stats_t.writeAc.miss;
|
|
homenode_tdp_stats = homenode_stats_t;
|
|
}
|
|
|
|
unicache.missb->stats_t.readAc.access = unicache.missb->l_ip.num_search_ports;
|
|
unicache.missb->stats_t.writeAc.access = unicache.missb->l_ip.num_search_ports;
|
|
unicache.missb->tdp_stats = unicache.missb->stats_t;
|
|
|
|
unicache.ifb->stats_t.readAc.access = unicache.ifb->l_ip.num_search_ports;
|
|
unicache.ifb->stats_t.writeAc.access = unicache.ifb->l_ip.num_search_ports;
|
|
unicache.ifb->tdp_stats = unicache.ifb->stats_t;
|
|
|
|
unicache.prefetchb->stats_t.readAc.access = unicache.prefetchb->l_ip.num_search_ports;
|
|
unicache.prefetchb->stats_t.writeAc.access = unicache.ifb->l_ip.num_search_ports;
|
|
unicache.prefetchb->tdp_stats = unicache.prefetchb->stats_t;
|
|
|
|
unicache.wbb->stats_t.readAc.access = unicache.wbb->l_ip.num_search_ports;
|
|
unicache.wbb->stats_t.writeAc.access = unicache.wbb->l_ip.num_search_ports;
|
|
unicache.wbb->tdp_stats = unicache.wbb->stats_t;
|
|
}
|
|
else
|
|
{
|
|
unicache.caches->stats_t.readAc.access = unicache.caches->l_ip.num_search_ports*cachep.duty_cycle;
|
|
unicache.caches->stats_t.readAc.miss = 0;
|
|
unicache.caches->stats_t.readAc.hit = unicache.caches->stats_t.readAc.access - unicache.caches->stats_t.readAc.miss;
|
|
unicache.caches->stats_t.writeAc.access = 0;
|
|
unicache.caches->stats_t.writeAc.miss = 0;
|
|
unicache.caches->stats_t.writeAc.hit = unicache.caches->stats_t.writeAc.access - unicache.caches->stats_t.writeAc.miss;
|
|
unicache.caches->tdp_stats = unicache.caches->stats_t;
|
|
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
//init stats for runtime power (RTP)
|
|
if (cacheL==L2)
|
|
{
|
|
unicache.caches->stats_t.readAc.access = XML->sys.L2[ithCache].read_accesses;
|
|
unicache.caches->stats_t.readAc.miss = XML->sys.L2[ithCache].read_misses;
|
|
unicache.caches->stats_t.readAc.hit = unicache.caches->stats_t.readAc.access - unicache.caches->stats_t.readAc.miss;
|
|
unicache.caches->stats_t.writeAc.access = XML->sys.L2[ithCache].write_accesses;
|
|
unicache.caches->stats_t.writeAc.miss = XML->sys.L2[ithCache].write_misses;
|
|
unicache.caches->stats_t.writeAc.hit = unicache.caches->stats_t.writeAc.access - unicache.caches->stats_t.writeAc.miss;
|
|
unicache.caches->rtp_stats = unicache.caches->stats_t;
|
|
|
|
if (cachep.dir_ty==SBT)
|
|
{
|
|
homenode_rtp_stats.readAc.access = XML->sys.L2[ithCache].homenode_read_accesses;
|
|
homenode_rtp_stats.readAc.miss = XML->sys.L2[ithCache].homenode_read_misses;
|
|
homenode_rtp_stats.readAc.hit = homenode_rtp_stats.readAc.access - homenode_rtp_stats.readAc.miss;
|
|
homenode_rtp_stats.writeAc.access = XML->sys.L2[ithCache].homenode_write_accesses;
|
|
homenode_rtp_stats.writeAc.miss = XML->sys.L2[ithCache].homenode_write_misses;
|
|
homenode_rtp_stats.writeAc.hit = homenode_rtp_stats.writeAc.access - homenode_rtp_stats.writeAc.miss;
|
|
}
|
|
}
|
|
else if (cacheL==L3)
|
|
{
|
|
unicache.caches->stats_t.readAc.access = XML->sys.L3[ithCache].read_accesses;
|
|
unicache.caches->stats_t.readAc.miss = XML->sys.L3[ithCache].read_misses;
|
|
unicache.caches->stats_t.readAc.hit = unicache.caches->stats_t.readAc.access - unicache.caches->stats_t.readAc.miss;
|
|
unicache.caches->stats_t.writeAc.access = XML->sys.L3[ithCache].write_accesses;
|
|
unicache.caches->stats_t.writeAc.miss = XML->sys.L3[ithCache].write_misses;
|
|
unicache.caches->stats_t.writeAc.hit = unicache.caches->stats_t.writeAc.access - unicache.caches->stats_t.writeAc.miss;
|
|
unicache.caches->rtp_stats = unicache.caches->stats_t;
|
|
|
|
if (cachep.dir_ty==SBT)
|
|
{
|
|
homenode_rtp_stats.readAc.access = XML->sys.L3[ithCache].homenode_read_accesses;
|
|
homenode_rtp_stats.readAc.miss = XML->sys.L3[ithCache].homenode_read_misses;
|
|
homenode_rtp_stats.readAc.hit = homenode_rtp_stats.readAc.access - homenode_rtp_stats.readAc.miss;
|
|
homenode_rtp_stats.writeAc.access = XML->sys.L3[ithCache].homenode_write_accesses;
|
|
homenode_rtp_stats.writeAc.miss = XML->sys.L3[ithCache].homenode_write_misses;
|
|
homenode_rtp_stats.writeAc.hit = homenode_rtp_stats.writeAc.access - homenode_rtp_stats.writeAc.miss;
|
|
}
|
|
}
|
|
else if (cacheL==L1Directory)
|
|
{
|
|
unicache.caches->stats_t.readAc.access = XML->sys.L1Directory[ithCache].read_accesses;
|
|
unicache.caches->stats_t.readAc.miss = XML->sys.L1Directory[ithCache].read_misses;
|
|
unicache.caches->stats_t.readAc.hit = unicache.caches->stats_t.readAc.access - unicache.caches->stats_t.readAc.miss;
|
|
unicache.caches->stats_t.writeAc.access = XML->sys.L1Directory[ithCache].write_accesses;
|
|
unicache.caches->stats_t.writeAc.miss = XML->sys.L1Directory[ithCache].write_misses;
|
|
unicache.caches->stats_t.writeAc.hit = unicache.caches->stats_t.writeAc.access - unicache.caches->stats_t.writeAc.miss;
|
|
unicache.caches->rtp_stats = unicache.caches->stats_t;
|
|
}
|
|
else if (cacheL==L2Directory)
|
|
{
|
|
unicache.caches->stats_t.readAc.access = XML->sys.L2Directory[ithCache].read_accesses;
|
|
unicache.caches->stats_t.readAc.miss = XML->sys.L2Directory[ithCache].read_misses;
|
|
unicache.caches->stats_t.readAc.hit = unicache.caches->stats_t.readAc.access - unicache.caches->stats_t.readAc.miss;
|
|
unicache.caches->stats_t.writeAc.access = XML->sys.L2Directory[ithCache].write_accesses;
|
|
unicache.caches->stats_t.writeAc.miss = XML->sys.L2Directory[ithCache].write_misses;
|
|
unicache.caches->stats_t.writeAc.hit = unicache.caches->stats_t.writeAc.access - unicache.caches->stats_t.writeAc.miss;
|
|
unicache.caches->rtp_stats = unicache.caches->stats_t;
|
|
}
|
|
if (!((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory)))
|
|
{ //Assuming write back and write-allocate cache
|
|
|
|
unicache.missb->stats_t.readAc.access = unicache.caches->stats_t.writeAc.miss ;
|
|
unicache.missb->stats_t.writeAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
unicache.missb->rtp_stats = unicache.missb->stats_t;
|
|
|
|
unicache.ifb->stats_t.readAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
unicache.ifb->stats_t.writeAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
unicache.ifb->rtp_stats = unicache.ifb->stats_t;
|
|
|
|
unicache.prefetchb->stats_t.readAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
unicache.prefetchb->stats_t.writeAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
unicache.prefetchb->rtp_stats = unicache.prefetchb->stats_t;
|
|
|
|
unicache.wbb->stats_t.readAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
unicache.wbb->stats_t.writeAc.access = unicache.caches->stats_t.writeAc.miss;
|
|
if (cachep.dir_ty==SBT)
|
|
{
|
|
unicache.missb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.missb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.missb->rtp_stats = unicache.missb->stats_t;
|
|
|
|
unicache.missb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.missb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.missb->rtp_stats = unicache.missb->stats_t;
|
|
|
|
unicache.ifb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.ifb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.ifb->rtp_stats = unicache.ifb->stats_t;
|
|
|
|
unicache.prefetchb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.prefetchb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.prefetchb->rtp_stats = unicache.prefetchb->stats_t;
|
|
|
|
unicache.wbb->stats_t.readAc.access += homenode_rtp_stats.writeAc.miss;
|
|
unicache.wbb->stats_t.writeAc.access += homenode_rtp_stats.writeAc.miss;
|
|
}
|
|
unicache.wbb->rtp_stats = unicache.wbb->stats_t;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
unicache.power_t.reset();
|
|
if (!((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory)))
|
|
{
|
|
unicache.power_t.readOp.dynamic += (unicache.caches->stats_t.readAc.hit*unicache.caches->local_result.power.readOp.dynamic+
|
|
unicache.caches->stats_t.readAc.miss*unicache.caches->local_result.tag_array2->power.readOp.dynamic+
|
|
unicache.caches->stats_t.writeAc.miss*unicache.caches->local_result.tag_array2->power.writeOp.dynamic+
|
|
unicache.caches->stats_t.writeAc.access*unicache.caches->local_result.power.writeOp.dynamic);//write miss will also generate a write later
|
|
|
|
if (cachep.dir_ty==SBT)
|
|
{
|
|
unicache.power_t.readOp.dynamic += homenode_stats_t.readAc.hit * (unicache.caches->local_result.data_array2->power.readOp.dynamic*dir_overhead +
|
|
unicache.caches->local_result.tag_array2->power.readOp.dynamic) +
|
|
homenode_stats_t.readAc.miss*unicache.caches->local_result.tag_array2->power.readOp.dynamic +
|
|
homenode_stats_t.writeAc.miss*unicache.caches->local_result.tag_array2->power.readOp.dynamic +
|
|
homenode_stats_t.writeAc.hit*(unicache.caches->local_result.data_array2->power.writeOp.dynamic*dir_overhead +
|
|
unicache.caches->local_result.tag_array2->power.readOp.dynamic+
|
|
homenode_stats_t.writeAc.miss*unicache.caches->local_result.power.writeOp.dynamic);//write miss on dynamic home node will generate a replacement write on whole cache block
|
|
|
|
|
|
}
|
|
|
|
unicache.power_t.readOp.dynamic += unicache.missb->stats_t.readAc.access*unicache.missb->local_result.power.searchOp.dynamic +
|
|
unicache.missb->stats_t.writeAc.access*unicache.missb->local_result.power.writeOp.dynamic;//each access to missb involves a CAM and a write
|
|
unicache.power_t.readOp.dynamic += unicache.ifb->stats_t.readAc.access*unicache.ifb->local_result.power.searchOp.dynamic +
|
|
unicache.ifb->stats_t.writeAc.access*unicache.ifb->local_result.power.writeOp.dynamic;
|
|
unicache.power_t.readOp.dynamic += unicache.prefetchb->stats_t.readAc.access*unicache.prefetchb->local_result.power.searchOp.dynamic +
|
|
unicache.prefetchb->stats_t.writeAc.access*unicache.prefetchb->local_result.power.writeOp.dynamic;
|
|
unicache.power_t.readOp.dynamic += unicache.wbb->stats_t.readAc.access*unicache.wbb->local_result.power.searchOp.dynamic +
|
|
unicache.wbb->stats_t.writeAc.access*unicache.wbb->local_result.power.writeOp.dynamic;
|
|
}
|
|
else
|
|
{
|
|
unicache.power_t.readOp.dynamic += (unicache.caches->stats_t.readAc.access*unicache.caches->local_result.power.searchOp.dynamic+
|
|
unicache.caches->stats_t.writeAc.access*unicache.caches->local_result.power.writeOp.dynamic);
|
|
}
|
|
|
|
if (is_tdp)
|
|
{
|
|
unicache.power = unicache.power_t + (unicache.caches->local_result.power)*pppm_lkg;
|
|
if (!((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory)))
|
|
{
|
|
unicache.power = unicache.power+
|
|
(unicache.missb->local_result.power +
|
|
unicache.ifb->local_result.power +
|
|
unicache.prefetchb->local_result.power +
|
|
unicache.wbb->local_result.power)*pppm_lkg;
|
|
}
|
|
power = power + unicache.power;
|
|
// cout<<"unicache.caches->local_result.power.readOp.dynamic"<<unicache.caches->local_result.power.readOp.dynamic<<endl;
|
|
// cout<<"unicache.caches->local_result.power.writeOp.dynamic"<<unicache.caches->local_result.power.writeOp.dynamic<<endl;
|
|
}
|
|
else
|
|
{
|
|
unicache.rt_power = unicache.power_t + (unicache.caches->local_result.power)*pppm_lkg;
|
|
if (!((cachep.dir_ty==ST&& cacheL==L1Directory)||(cachep.dir_ty==ST&& cacheL==L2Directory)))
|
|
{
|
|
(unicache.rt_power = unicache.rt_power +
|
|
unicache.missb->local_result.power +
|
|
unicache.ifb->local_result.power +
|
|
unicache.prefetchb->local_result.power +
|
|
unicache.wbb->local_result.power)*pppm_lkg;
|
|
}
|
|
rt_power = rt_power + unicache.rt_power;
|
|
}
|
|
}
|
|
|
|
void SharedCache::displayEnergy(uint32_t indent,bool is_tdp)
|
|
{
|
|
string indent_str(indent, ' ');
|
|
string indent_str_next(indent+2, ' ');
|
|
bool long_channel = XML->sys.longer_channel_device;
|
|
|
|
if (is_tdp)
|
|
{
|
|
cout << (XML->sys.Private_L2? indent_str:"")<< cachep.name << endl;
|
|
cout << indent_str << "Area = " << area.get_area()*1e-6<< " mm^2" << endl;
|
|
cout << indent_str << "Peak Dynamic = " << power.readOp.dynamic*cachep.clockRate << " W" << endl;
|
|
cout << indent_str << "Subthreshold Leakage = "
|
|
<< (long_channel? power.readOp.longer_channel_leakage:power.readOp.leakage) <<" W" << endl;
|
|
//cout << indent_str << "Subthreshold Leakage = " << power.readOp.longer_channel_leakage <<" W" << endl;
|
|
cout << indent_str << "Gate Leakage = " << power.readOp.gate_leakage << " W" << endl;
|
|
cout << indent_str << "Runtime Dynamic = " << rt_power.readOp.dynamic/cachep.executionTime << " W" << endl;
|
|
cout <<endl;
|
|
}
|
|
else
|
|
{
|
|
}
|
|
}
|
|
|
|
//void SharedCache::computeMaxPower()
|
|
//{
|
|
// //Compute maximum power and runtime power.
|
|
// //When computing runtime power, McPAT gets or reasons out the statistics based on XML input.
|
|
// maxPower = 0.0;
|
|
// //llCache,itlb
|
|
// llCache.maxPower = 0.0;
|
|
// llCache.maxPower += (llCache.caches.l_ip.num_rw_ports*(0.67*llCache.caches.local_result.power.readOp.dynamic+0.33*llCache.caches.local_result.power.writeOp.dynamic)
|
|
// +llCache.caches.l_ip.num_rd_ports*llCache.caches.local_result.power.readOp.dynamic+llCache.caches.l_ip.num_wr_ports*llCache.caches.local_result.power.writeOp.dynamic
|
|
// +llCache.caches.l_ip.num_se_rd_ports*llCache.caches.local_result.power.readOp.dynamic)*clockRate;
|
|
// ///cout<<"llCache.maxPower=" <<llCache.maxPower<<endl;
|
|
//
|
|
// llCache.maxPower += llCache.missb.l_ip.num_search_ports*llCache.missb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"llCache.maxPower=" <<llCache.maxPower<<endl;
|
|
//
|
|
// llCache.maxPower += llCache.ifb.l_ip.num_search_ports*llCache.ifb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"llCache.maxPower=" <<llCache.maxPower<<endl;
|
|
//
|
|
// llCache.maxPower += llCache.prefetchb.l_ip.num_search_ports*llCache.prefetchb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"llCache.maxPower=" <<llCache.maxPower<<endl;
|
|
//
|
|
// llCache.maxPower += llCache.wbb.l_ip.num_search_ports*llCache.wbb.local_result.power.searchOp.dynamic*clockRate;
|
|
// //llCache.maxPower *= scktRatio; //TODO: this calculation should be self-contained
|
|
// ///cout<<"llCache.maxPower=" <<llCache.maxPower<<endl;
|
|
//
|
|
//// directory_power = (directory.caches.l_ip.num_rw_ports*(0.67*directory.caches.local_result.power.readOp.dynamic+0.33*directory.caches.local_result.power.writeOp.dynamic)
|
|
//// +directory.caches.l_ip.num_rd_ports*directory.caches.local_result.power.readOp.dynamic+directory.caches.l_ip.num_wr_ports*directory.caches.local_result.power.writeOp.dynamic
|
|
//// +directory.caches.l_ip.num_se_rd_ports*directory.caches.local_result.power.readOp.dynamic)*clockRate;
|
|
//
|
|
// L2Tot.power.readOp.dynamic = llCache.maxPower;
|
|
// L2Tot.power.readOp.leakage = llCache.caches.local_result.power.readOp.leakage +
|
|
// llCache.missb.local_result.power.readOp.leakage +
|
|
// llCache.ifb.local_result.power.readOp.leakage +
|
|
// llCache.prefetchb.local_result.power.readOp.leakage +
|
|
// llCache.wbb.local_result.power.readOp.leakage;
|
|
//
|
|
// L2Tot.area.set_area(llCache.area*1.1*1e-6);//placement and routing overhead
|
|
//
|
|
// if (XML->sys.number_of_dir_levels==1)
|
|
// {
|
|
// if (XML->sys.first_level_dir==0)
|
|
// {
|
|
// directory.maxPower = 0.0;
|
|
// directory.maxPower += (directory.caches.l_ip.num_rw_ports*(0.67*directory.caches.local_result.power.readOp.dynamic+0.33*directory.caches.local_result.power.writeOp.dynamic)
|
|
// +directory.caches.l_ip.num_rd_ports*directory.caches.local_result.power.readOp.dynamic+directory.caches.l_ip.num_wr_ports*directory.caches.local_result.power.writeOp.dynamic
|
|
// +directory.caches.l_ip.num_se_rd_ports*directory.caches.local_result.power.readOp.dynamic)*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.missb.l_ip.num_search_ports*directory.missb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.ifb.l_ip.num_search_ports*directory.ifb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.prefetchb.l_ip.num_search_ports*directory.prefetchb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.wbb.l_ip.num_search_ports*directory.wbb.local_result.power.searchOp.dynamic*clockRate;
|
|
//
|
|
// cc.power.readOp.dynamic = directory.maxPower*scktRatio*8;//8 is the memory controller counts
|
|
// cc.power.readOp.leakage = directory.caches.local_result.power.readOp.leakage +
|
|
// directory.missb.local_result.power.readOp.leakage +
|
|
// directory.ifb.local_result.power.readOp.leakage +
|
|
// directory.prefetchb.local_result.power.readOp.leakage +
|
|
// directory.wbb.local_result.power.readOp.leakage;
|
|
//
|
|
// cc.power.readOp.leakage *=8;
|
|
//
|
|
// cc.area.set_area(directory.area*8);
|
|
// cout<<"CC area="<<cc.area.get_area()*1e-6<<endl;
|
|
// cout<<"CC Power="<<cc.power.readOp.dynamic<<endl;
|
|
// ccTot.area.set_area(cc.area.get_area()*1e-6);
|
|
// ccTot.power = cc.power;
|
|
// cout<<"DC energy per access" << cc.power.readOp.dynamic/clockRate/8;
|
|
// }
|
|
// else if (XML->sys.first_level_dir==1)
|
|
// {
|
|
// inv_dir.maxPower = inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size;
|
|
// cc.power.readOp.dynamic = inv_dir.maxPower*scktRatio*64/XML->sys.domain_size;
|
|
// cc.power.readOp.leakage = inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*64/XML->sys.domain_size;
|
|
//
|
|
// cc.area.set_area(inv_dir.area*64/XML->sys.domain_size);
|
|
// cout<<"CC area="<<cc.area.get_area()*1e-6<<endl;
|
|
// cout<<"CC Power="<<cc.power.readOp.dynamic<<endl;
|
|
// ccTot.area.set_area(cc.area.get_area()*1e-6);
|
|
// cout<<"DC energy per access" << cc.power.readOp.dynamic/clockRate/8;
|
|
// ccTot.power = cc.power;
|
|
// }
|
|
// }
|
|
//
|
|
// else if (XML->sys.number_of_dir_levels==2)
|
|
// {
|
|
//
|
|
// directory.maxPower = 0.0;
|
|
// directory.maxPower += (directory.caches.l_ip.num_rw_ports*(0.67*directory.caches.local_result.power.readOp.dynamic+0.33*directory.caches.local_result.power.writeOp.dynamic)
|
|
// +directory.caches.l_ip.num_rd_ports*directory.caches.local_result.power.readOp.dynamic+directory.caches.l_ip.num_wr_ports*directory.caches.local_result.power.writeOp.dynamic
|
|
// +directory.caches.l_ip.num_se_rd_ports*directory.caches.local_result.power.readOp.dynamic)*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.missb.l_ip.num_search_ports*directory.missb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.ifb.l_ip.num_search_ports*directory.ifb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.prefetchb.l_ip.num_search_ports*directory.prefetchb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
|
|
//
|
|
// directory.maxPower += directory.wbb.l_ip.num_search_ports*directory.wbb.local_result.power.searchOp.dynamic*clockRate;
|
|
//
|
|
// cc.power.readOp.dynamic = directory.maxPower*scktRatio*8;//8 is the memory controller counts
|
|
// cc.power.readOp.leakage = directory.caches.local_result.power.readOp.leakage +
|
|
// directory.missb.local_result.power.readOp.leakage +
|
|
// directory.ifb.local_result.power.readOp.leakage +
|
|
// directory.prefetchb.local_result.power.readOp.leakage +
|
|
// directory.wbb.local_result.power.readOp.leakage;
|
|
// cc.power.readOp.leakage *=8;
|
|
// cc.area.set_area(directory.area*8);
|
|
//
|
|
// if (XML->sys.first_level_dir==0)
|
|
// {
|
|
// directory1.maxPower = 0.0;
|
|
// directory1.maxPower += (directory1.caches.l_ip.num_rw_ports*(0.67*directory1.caches.local_result.power.readOp.dynamic+0.33*directory1.caches.local_result.power.writeOp.dynamic)
|
|
// +directory1.caches.l_ip.num_rd_ports*directory1.caches.local_result.power.readOp.dynamic+directory1.caches.l_ip.num_wr_ports*directory1.caches.local_result.power.writeOp.dynamic
|
|
// +directory1.caches.l_ip.num_se_rd_ports*directory1.caches.local_result.power.readOp.dynamic)*clockRate;
|
|
// ///cout<<"directory1.maxPower=" <<directory1.maxPower<<endl;
|
|
//
|
|
// directory1.maxPower += directory1.missb.l_ip.num_search_ports*directory1.missb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory1.maxPower=" <<directory1.maxPower<<endl;
|
|
//
|
|
// directory1.maxPower += directory1.ifb.l_ip.num_search_ports*directory1.ifb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory1.maxPower=" <<directory1.maxPower<<endl;
|
|
//
|
|
// directory1.maxPower += directory1.prefetchb.l_ip.num_search_ports*directory1.prefetchb.local_result.power.searchOp.dynamic*clockRate;
|
|
// ///cout<<"directory1.maxPower=" <<directory1.maxPower<<endl;
|
|
//
|
|
// directory1.maxPower += directory1.wbb.l_ip.num_search_ports*directory1.wbb.local_result.power.searchOp.dynamic*clockRate;
|
|
//
|
|
// cc1.power.readOp.dynamic = directory1.maxPower*scktRatio*64/XML->sys.domain_size;
|
|
// cc1.power.readOp.leakage = directory1.caches.local_result.power.readOp.leakage +
|
|
// directory1.missb.local_result.power.readOp.leakage +
|
|
// directory1.ifb.local_result.power.readOp.leakage +
|
|
// directory1.prefetchb.local_result.power.readOp.leakage +
|
|
// directory1.wbb.local_result.power.readOp.leakage;
|
|
// cc1.power.readOp.leakage *= 64/XML->sys.domain_size;
|
|
// cc1.area.set_area(directory1.area*64/XML->sys.domain_size);
|
|
//
|
|
// cout<<"CC area="<<(cc.area.get_area()+cc1.area.get_area())*1e-6<<endl;
|
|
// cout<<"CC Power="<<cc.power.readOp.dynamic + cc1.power.readOp.dynamic <<endl;
|
|
// ccTot.area.set_area((cc.area.get_area()+cc1.area.get_area())*1e-6);
|
|
// ccTot.power = cc.power + cc1.power;
|
|
// }
|
|
// else if (XML->sys.first_level_dir==1)
|
|
// {
|
|
// inv_dir.maxPower = inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size;
|
|
// cc1.power.readOp.dynamic = inv_dir.maxPower*scktRatio*(64/XML->sys.domain_size);
|
|
// cc1.power.readOp.leakage = inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*XML->sys.domain_size;
|
|
//
|
|
// cc1.area.set_area(inv_dir.area*64/XML->sys.domain_size);
|
|
// cout<<"CC area="<<(cc.area.get_area()+cc1.area.get_area())*1e-6<<endl;
|
|
// cout<<"CC Power="<<cc.power.readOp.dynamic + cc1.power.readOp.dynamic <<endl;
|
|
// ccTot.area.set_area((cc.area.get_area()+cc1.area.get_area())*1e-6);
|
|
// ccTot.power = cc.power + cc1.power;
|
|
//
|
|
// }
|
|
// else if (XML->sys.first_level_dir==2)
|
|
// {
|
|
// cout<<"CC area="<<cc.area.get_area()*1e-6<<endl;
|
|
// cout<<"CC Power="<<cc.power.readOp.dynamic<<endl;
|
|
// ccTot.area.set_area(cc.area.get_area()*1e-6);
|
|
// ccTot.power = cc.power;
|
|
// }
|
|
// }
|
|
//
|
|
//cout<<"L2cache size="<<L2Tot.area.get_area()*1e-6<<endl;
|
|
//cout<<"L2cache dynamic power="<<L2Tot.power.readOp.dynamic<<endl;
|
|
//cout<<"L2cache laeakge power="<<L2Tot.power.readOp.leakage<<endl;
|
|
//
|
|
// ///cout<<"llCache.maxPower=" <<llCache.maxPower<<endl;
|
|
//
|
|
//
|
|
// maxPower += llCache.maxPower;
|
|
// ///cout<<"maxpower=" <<maxPower<<endl;
|
|
//
|
|
//// maxPower += pipeLogicCache.power.readOp.dynamic*clockRate;
|
|
//// ///cout<<"pipeLogic.power="<<pipeLogicCache.power.readOp.dynamic*clockRate<<endl;
|
|
//// ///cout<<"maxpower=" <<maxPower<<endl;
|
|
////
|
|
//// maxPower += pipeLogicDirectory.power.readOp.dynamic*clockRate;
|
|
//// ///cout<<"pipeLogic.power="<<pipeLogicDirectory.power.readOp.dynamic*clockRate<<endl;
|
|
//// ///cout<<"maxpower=" <<maxPower<<endl;
|
|
////
|
|
//// //clock power
|
|
//// maxPower += clockNetwork.total_power.readOp.dynamic*clockRate;
|
|
//// ///cout<<"clockNetwork.total_power="<<clockNetwork.total_power.readOp.dynamic*clockRate<<endl;
|
|
//// ///cout<<"maxpower=" <<maxPower<<endl;
|
|
//
|
|
//}
|
|
|
|
void SharedCache::set_cache_param()
|
|
{
|
|
if (cacheL==L2)
|
|
{
|
|
cachep.name = "L2";
|
|
cachep.clockRate = XML->sys.L2[ithCache].clockrate;
|
|
cachep.clockRate *= 1e6;
|
|
cachep.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
|
|
interface_ip.data_arr_ram_cell_tech_type = XML->sys.L2[ithCache].device_type;//long channel device LSTP
|
|
interface_ip.data_arr_peri_global_tech_type = XML->sys.L2[ithCache].device_type;
|
|
interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L2[ithCache].device_type;
|
|
interface_ip.tag_arr_peri_global_tech_type = XML->sys.L2[ithCache].device_type;
|
|
cachep.capacity = XML->sys.L2[ithCache].L2_config[0];
|
|
cachep.blockW = XML->sys.L2[ithCache].L2_config[1];
|
|
cachep.assoc = XML->sys.L2[ithCache].L2_config[2];
|
|
cachep.nbanks = XML->sys.L2[ithCache].L2_config[3];
|
|
cachep.throughput = XML->sys.L2[ithCache].L2_config[4]/cachep.clockRate;
|
|
cachep.latency = XML->sys.L2[ithCache].L2_config[5]/cachep.clockRate;
|
|
cachep.missb_size = XML->sys.L2[ithCache].buffer_sizes[0];
|
|
cachep.fu_size = XML->sys.L2[ithCache].buffer_sizes[1];
|
|
cachep.prefetchb_size= XML->sys.L2[ithCache].buffer_sizes[2];
|
|
cachep.wbb_size = XML->sys.L2[ithCache].buffer_sizes[3];
|
|
cachep.duty_cycle = XML->sys.L2[ithCache].duty_cycle;
|
|
if (!XML->sys.L2[ithCache].merged_dir)
|
|
{
|
|
cachep.dir_ty = NonDir;
|
|
}
|
|
else
|
|
{
|
|
cachep.dir_ty = SBT;
|
|
cachep.dir_duty_cycle = XML->sys.L2[ithCache].dir_duty_cycle;
|
|
}
|
|
}
|
|
else if (cacheL==L3)
|
|
{
|
|
cachep.name = "L3";
|
|
cachep.clockRate = XML->sys.L3[ithCache].clockrate;
|
|
cachep.clockRate *= 1e6;
|
|
cachep.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
|
|
interface_ip.data_arr_ram_cell_tech_type = XML->sys.L3[ithCache].device_type;//long channel device LSTP
|
|
interface_ip.data_arr_peri_global_tech_type = XML->sys.L3[ithCache].device_type;
|
|
interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L3[ithCache].device_type;
|
|
interface_ip.tag_arr_peri_global_tech_type = XML->sys.L3[ithCache].device_type;
|
|
cachep.capacity = XML->sys.L3[ithCache].L3_config[0];
|
|
cachep.blockW = XML->sys.L3[ithCache].L3_config[1];
|
|
cachep.assoc = XML->sys.L3[ithCache].L3_config[2];
|
|
cachep.nbanks = XML->sys.L3[ithCache].L3_config[3];
|
|
cachep.throughput = XML->sys.L3[ithCache].L3_config[4]/cachep.clockRate;
|
|
cachep.latency = XML->sys.L3[ithCache].L3_config[5]/cachep.clockRate;
|
|
cachep.missb_size = XML->sys.L3[ithCache].buffer_sizes[0];
|
|
cachep.fu_size = XML->sys.L3[ithCache].buffer_sizes[1];
|
|
cachep.prefetchb_size= XML->sys.L3[ithCache].buffer_sizes[2];
|
|
cachep.wbb_size = XML->sys.L3[ithCache].buffer_sizes[3];
|
|
cachep.duty_cycle = XML->sys.L3[ithCache].duty_cycle;
|
|
if (!XML->sys.L2[ithCache].merged_dir)
|
|
{
|
|
cachep.dir_ty = NonDir;
|
|
}
|
|
else
|
|
{
|
|
cachep.dir_ty = SBT;
|
|
cachep.dir_duty_cycle = XML->sys.L2[ithCache].dir_duty_cycle;
|
|
}
|
|
}
|
|
else if (cacheL==L1Directory)
|
|
{
|
|
cachep.name = "First Level Directory";
|
|
cachep.dir_ty = (enum Dir_type) XML->sys.L1Directory[ithCache].Directory_type;
|
|
cachep.clockRate = XML->sys.L1Directory[ithCache].clockrate;
|
|
cachep.clockRate *= 1e6;
|
|
cachep.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
|
|
interface_ip.data_arr_ram_cell_tech_type = XML->sys.L1Directory[ithCache].device_type;//long channel device LSTP
|
|
interface_ip.data_arr_peri_global_tech_type = XML->sys.L1Directory[ithCache].device_type;
|
|
interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L1Directory[ithCache].device_type;
|
|
interface_ip.tag_arr_peri_global_tech_type = XML->sys.L1Directory[ithCache].device_type;
|
|
cachep.capacity = XML->sys.L1Directory[ithCache].Dir_config[0];
|
|
cachep.blockW = XML->sys.L1Directory[ithCache].Dir_config[1];
|
|
cachep.assoc = XML->sys.L1Directory[ithCache].Dir_config[2];
|
|
cachep.nbanks = XML->sys.L1Directory[ithCache].Dir_config[3];
|
|
cachep.throughput = XML->sys.L1Directory[ithCache].Dir_config[4]/cachep.clockRate;
|
|
cachep.latency = XML->sys.L1Directory[ithCache].Dir_config[5]/cachep.clockRate;
|
|
cachep.missb_size = XML->sys.L1Directory[ithCache].buffer_sizes[0];
|
|
cachep.fu_size = XML->sys.L1Directory[ithCache].buffer_sizes[1];
|
|
cachep.prefetchb_size= XML->sys.L1Directory[ithCache].buffer_sizes[2];
|
|
cachep.wbb_size = XML->sys.L1Directory[ithCache].buffer_sizes[3];
|
|
cachep.duty_cycle = XML->sys.L1Directory[ithCache].duty_cycle;
|
|
}
|
|
else if (cacheL==L2Directory)
|
|
{
|
|
cachep.name = "Second Level Directory";
|
|
cachep.dir_ty = (enum Dir_type) XML->sys.L2Directory[ithCache].Directory_type;
|
|
cachep.clockRate = XML->sys.L2Directory[ithCache].clockrate;
|
|
cachep.clockRate *= 1e6;
|
|
cachep.executionTime = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
|
|
interface_ip.data_arr_ram_cell_tech_type = XML->sys.L2Directory[ithCache].device_type;//long channel device LSTP
|
|
interface_ip.data_arr_peri_global_tech_type = XML->sys.L2Directory[ithCache].device_type;
|
|
interface_ip.tag_arr_ram_cell_tech_type = XML->sys.L2Directory[ithCache].device_type;
|
|
interface_ip.tag_arr_peri_global_tech_type = XML->sys.L2Directory[ithCache].device_type;
|
|
cachep.capacity = XML->sys.L2Directory[ithCache].Dir_config[0];
|
|
cachep.blockW = XML->sys.L2Directory[ithCache].Dir_config[1];
|
|
cachep.assoc = XML->sys.L2Directory[ithCache].Dir_config[2];
|
|
cachep.nbanks = XML->sys.L2Directory[ithCache].Dir_config[3];
|
|
cachep.throughput = XML->sys.L2Directory[ithCache].Dir_config[4]/cachep.clockRate;
|
|
cachep.latency = XML->sys.L2Directory[ithCache].Dir_config[5]/cachep.clockRate;
|
|
cachep.missb_size = XML->sys.L2Directory[ithCache].buffer_sizes[0];
|
|
cachep.fu_size = XML->sys.L2Directory[ithCache].buffer_sizes[1];
|
|
cachep.prefetchb_size= XML->sys.L2Directory[ithCache].buffer_sizes[2];
|
|
cachep.wbb_size = XML->sys.L2Directory[ithCache].buffer_sizes[3];
|
|
cachep.duty_cycle = XML->sys.L2Directory[ithCache].duty_cycle;
|
|
}
|
|
//cachep.cache_duty_cycle=cachep.dir_duty_cycle = 0.35;
|
|
}
|
|
|