gem5/src
Ali Saidi 649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
..
arch LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
base Stats: Add a sparse histogram stat object. 2011-08-19 15:08:05 -05:00
cpu LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
dev ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
mem Stack: Tidy up some comments, a warning, and make stack extension consistent. 2011-09-09 01:01:43 -07:00
python Stats: Add a sparse histogram stat object. 2011-08-19 15:08:05 -05:00
sim LSQ: Only trigger a memory violation with a load/load if the value changes. 2011-09-13 12:58:08 -04:00
unittest Stats: Add a sparse histogram stat object. 2011-08-19 15:08:05 -05:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00