gem5/arch/mips/isa/operands.isa
Korey Sewell d30262d480 name changes ... minor IntOP format change
arch/mips/isa/formats/int.format:
    Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
    their reg-reg counterparts

--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
2006-02-07 18:36:08 -05:00

36 lines
1.3 KiB
Text

def operand_types {{
'sb' : ('signed int', 8),
'ub' : ('unsigned int', 8),
'shw' : ('signed int', 16),
'uhw' : ('unsigned int', 16),
'sw' : ('signed int', 32),
'uw' : ('unsigned int', 32),
'sdw' : ('signed int', 64),
'udw' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64),
'qf' : ('float', 128)
}};
def operands {{
'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1),
'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),
'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3),
'Mem': MemOperandTraits('udw', None,
('IsMemRef', 'IsLoad', 'IsStore'), 4)
#'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
#'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
#'R0': IntRegOperandTraits('uq', '0', None, 1),
#'R16': IntRegOperandTraits('uq', '16', None, 1)
}};