93839380e7
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset
configs/test/fs.py:
Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
change naming for pio port
break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
src/dev/sinic.cc:
remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
add idea of default responder to bus
src/python/m5/objects/Pci.py:
add config port for pci devices
add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)
--HG--
extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
368 lines
11 KiB
C++
368 lines
11 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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*/
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/** @file
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* Tsunami PChip (pci)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/packet.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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//Should this be AlphaISA?
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using namespace TheISA;
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TsunamiPChip::TsunamiPChip(Params *p)
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: BasicPioDevice(p)
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{
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pioSize = 0xfff;
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for (int i = 0; i < 4; i++) {
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wsba[i] = 0;
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wsm[i] = 0;
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tba[i] = 0;
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}
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// initialize pchip control register
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pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
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//Set back pointer in tsunami
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p->tsunami->pchip = this;
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}
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Tick
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TsunamiPChip::read(Packet *pkt)
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{
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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pkt->allocate();
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Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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pkt->set(wsba[0]);
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break;
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case TSDEV_PC_WSBA1:
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pkt->set(wsba[1]);
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break;
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case TSDEV_PC_WSBA2:
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pkt->set(wsba[2]);
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break;
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case TSDEV_PC_WSBA3:
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pkt->set(wsba[3]);
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break;
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case TSDEV_PC_WSM0:
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pkt->set(wsm[0]);
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break;
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case TSDEV_PC_WSM1:
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pkt->set(wsm[1]);
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break;
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case TSDEV_PC_WSM2:
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pkt->set(wsm[2]);
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break;
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case TSDEV_PC_WSM3:
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pkt->set(wsm[3]);
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break;
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case TSDEV_PC_TBA0:
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pkt->set(tba[0]);
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break;
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case TSDEV_PC_TBA1:
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pkt->set(tba[1]);
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break;
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case TSDEV_PC_TBA2:
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pkt->set(tba[2]);
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break;
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case TSDEV_PC_TBA3:
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pkt->set(tba[3]);
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break;
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case TSDEV_PC_PCTL:
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pkt->set(pctl);
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break;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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pkt->set((uint64_t)0x00);
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break;
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case TSDEV_PC_PERRMASK:
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pkt->set((uint64_t)0x00);
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break;
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
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break;
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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}
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pkt->result = Packet::Success;
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return pioDelay;
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}
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Tick
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TsunamiPChip::write(Packet *pkt)
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{
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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wsba[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA1:
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wsba[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA2:
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wsba[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA3:
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wsba[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM0:
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wsm[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM1:
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wsm[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM2:
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wsm[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM3:
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wsm[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA0:
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tba[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA1:
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tba[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA2:
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tba[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA3:
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tba[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_PCTL:
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pctl = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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break;
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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break; // value ignored, supposted to invalidate SG TLB
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip write reached reading 0x%x\n", daddr);
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} // uint64_t
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pkt->result = Packet::Success;
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return pioDelay;
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}
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#define DMA_ADDR_MASK ULL(0x3ffffffff)
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Addr
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TsunamiPChip::translatePciToDma(Addr busAddr)
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{
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// compare the address to the window base registers
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uint64_t tbaMask = 0;
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uint64_t baMask = 0;
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uint64_t windowMask = 0;
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uint64_t windowBase = 0;
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uint64_t pteEntry = 0;
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Addr pteAddr;
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Addr dmaAddr;
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#if 0
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DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
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for (int i = 0; i < 4; i++) {
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DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
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i, wsba[i], wsm[i]);
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
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i, windowBase, windowMask, (busAddr & windowMask),
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(windowBase & windowMask));
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}
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}
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#endif
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for (int i = 0; i < 4; i++) {
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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if (wsba[i] & 0x1) { // see if enabled
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if (wsba[i] & 0x2) { // see if SG bit is set
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/** @todo
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This currently is faked by just doing a direct
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read from memory, however, to be realistic, this
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needs to actually do a bus transaction. The process
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is explained in the tsunami documentation on page
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10-12 and basically munges the address to look up a
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PTE from a table in memory and then uses that mapping
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to create an address for the SG page
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*/
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tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
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pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
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pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
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dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
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} else {
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
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tbaMask = ~baMask;
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dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
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}
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return (dmaAddr & DMA_ADDR_MASK);
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}
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}
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}
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// if no match was found, then return the original address
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return busAddr;
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}
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Addr
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TsunamiPChip::calcConfigAddr(int bus, int dev, int func)
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{
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assert(func < 8);
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assert(dev < 32);
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assert(bus == 0);
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return TsunamiPciBus0Config | (func << 8) | (dev << 11);
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}
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void
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TsunamiPChip::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(pctl);
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SERIALIZE_ARRAY(wsba, 4);
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SERIALIZE_ARRAY(wsm, 4);
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SERIALIZE_ARRAY(tba, 4);
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}
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void
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TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(pctl);
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UNSERIALIZE_ARRAY(wsba, 4);
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UNSERIALIZE_ARRAY(wsm, 4);
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UNSERIALIZE_ARRAY(tba, 4);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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Param<Addr> pio_addr;
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Param<Tick> pio_latency;
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SimObjectParam<Platform *> platform;
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SimObjectParam<System *> system;
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SimObjectParam<Tsunami *> tsunami;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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INIT_PARAM(pio_addr, "Device Address"),
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INIT_PARAM(pio_latency, "Programmed IO latency"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(tsunami, "Tsunami")
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END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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CREATE_SIM_OBJECT(TsunamiPChip)
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{
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TsunamiPChip::Params *p = new TsunamiPChip::Params;
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p->name = getInstanceName();
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p->pio_addr = pio_addr;
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p->pio_delay = pio_latency;
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p->platform = platform;
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p->system = system;
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p->tsunami = tsunami;
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return new TsunamiPChip(p);
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}
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REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
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