eb0e416998
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.
src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
Change ExecContext to ThreadContext.
--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
553 lines
17 KiB
C++
553 lines
17 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Ron Dreslinski
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*/
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/** @file
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* Emulation of the Tsunami CChip CSRs
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "arch/alpha/ev5.hh"
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#include "base/trace.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/port.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/intr_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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//Should this be AlphaISA?
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using namespace TheISA;
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TsunamiCChip::TsunamiCChip(Params *p)
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: BasicPioDevice(p), tsunami(p->tsunami)
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{
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pioSize = 0xfffffff;
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drir = 0;
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ipint = 0;
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itint = 0;
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for (int x = 0; x < Tsunami::Max_CPUs; x++)
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{
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dim[x] = 0;
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dir[x] = 0;
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}
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//Put back pointer in tsunami
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tsunami->cchip = this;
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}
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Tick
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TsunamiCChip::read(Packet *pkt)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
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Addr daddr = (pkt->getAddr() - pioAddr);
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pkt->allocate();
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switch (pkt->getSize()) {
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case sizeof(uint64_t):
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if (daddr & TSDEV_CC_BDIMS)
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{
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pkt->set(dim[(daddr >> 4) & 0x3F]);
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break;
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}
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if (daddr & TSDEV_CC_BDIRS)
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{
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pkt->set(dir[(daddr >> 4) & 0x3F]);
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break;
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}
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switch(regnum) {
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case TSDEV_CC_CSR:
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pkt->set(0x0);
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break;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR not implemeted\n");
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break;
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case TSDEV_CC_MISC:
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pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
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(pkt->req->getCpuNum() & 0x3));
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break;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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pkt->set(0);
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break;
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case TSDEV_CC_DIM0:
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pkt->set(dim[0]);
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break;
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case TSDEV_CC_DIM1:
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pkt->set(dim[1]);
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break;
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case TSDEV_CC_DIM2:
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pkt->set(dim[2]);
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break;
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case TSDEV_CC_DIM3:
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pkt->set(dim[3]);
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break;
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case TSDEV_CC_DIR0:
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pkt->set(dir[0]);
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break;
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case TSDEV_CC_DIR1:
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pkt->set(dir[1]);
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break;
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case TSDEV_CC_DIR2:
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pkt->set(dir[2]);
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break;
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case TSDEV_CC_DIR3:
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pkt->set(dir[3]);
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break;
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case TSDEV_CC_DRIR:
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pkt->set(drir);
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break;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN not implemented\n");
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break;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx not implemented\n");
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break;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx not implemented\n");
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break;
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case TSDEV_CC_IPIR:
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pkt->set(ipint);
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break;
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case TSDEV_CC_ITIR:
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pkt->set(itint);
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break;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
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regnum, pkt->getSize(), pkt->get<uint64_t>());
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pkt->result = Packet::Success;
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return pioDelay;
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}
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Tick
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TsunamiCChip::write(Packet *pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
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bool supportedWrite = false;
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if (daddr & TSDEV_CC_BDIMS)
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{
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int number = (daddr >> 4) & 0x3F;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = pkt->get<uint64_t>();
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dir[number] = dim[number] & drir;
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for(int x = 0; x < Tsunami::Max_CPUs; x++)
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{
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bitvector = ULL(1) << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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// The bit is now set and it wasn't before (set)
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if((dim[number] & bitvector) && (dir[number] & bitvector))
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{
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in posting dir"
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" interrupt to cpu %d\n", number);
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}
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in clear"
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" dir interrupt to cpu %d\n", number);
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}
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}
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}
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} else {
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switch(regnum) {
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case TSDEV_CC_CSR:
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panic("TSDEV_CC_CSR write\n");
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR write not implemented\n");
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case TSDEV_CC_MISC:
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uint64_t ipreq;
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ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
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//If it is bit 12-15, this is an IPI post
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if (ipreq) {
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reqIPI(ipreq);
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supportedWrite = true;
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}
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//If it is bit 8-11, this is an IPI clear
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uint64_t ipintr;
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ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
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if (ipintr) {
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clearIPI(ipintr);
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supportedWrite = true;
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}
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//If it is the 4-7th bit, clear the RTC interrupt
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uint64_t itintr;
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itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
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if (itintr) {
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clearITI(itintr);
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supportedWrite = true;
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}
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// ignore NXMs
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if (pkt->get<uint64_t>() & 0x10000000)
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supportedWrite = true;
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if(!supportedWrite)
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panic("TSDEV_CC_MISC write not implemented\n");
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break;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx write not implemeted\n");
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case TSDEV_CC_DIM0:
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case TSDEV_CC_DIM1:
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case TSDEV_CC_DIM2:
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case TSDEV_CC_DIM3:
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int number;
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if(regnum == TSDEV_CC_DIM0)
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number = 0;
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else if(regnum == TSDEV_CC_DIM1)
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number = 1;
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else if(regnum == TSDEV_CC_DIM2)
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number = 2;
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else
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number = 3;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = pkt->get<uint64_t>();
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dir[number] = dim[number] & drir;
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for(int x = 0; x < 64; x++)
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{
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bitvector = ULL(1) << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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// The bit is now set and it wasn't before (set)
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if((dim[number] & bitvector) && (dir[number] & bitvector))
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{
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
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}
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in clear"
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" dir interrupt to cpu %d\n",
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x);
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}
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}
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}
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break;
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case TSDEV_CC_DIR0:
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case TSDEV_CC_DIR1:
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case TSDEV_CC_DIR2:
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case TSDEV_CC_DIR3:
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panic("TSDEV_CC_DIR write not implemented\n");
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case TSDEV_CC_DRIR:
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panic("TSDEV_CC_DRIR write not implemented\n");
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN write not implemented\n");
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx write not implemented\n");
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx write not implemented\n");
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case TSDEV_CC_IPIR:
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clearIPI(pkt->get<uint64_t>());
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break;
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case TSDEV_CC_ITIR:
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clearITI(pkt->get<uint64_t>());
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break;
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case TSDEV_CC_IPIQ:
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reqIPI(pkt->get<uint64_t>());
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break;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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} // swtich(regnum)
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} // not BIG_TSUNAMI write
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pkt->result = Packet::Success;
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return pioDelay;
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}
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void
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TsunamiCChip::clearIPI(uint64_t ipintr)
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{
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int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
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assert(numcpus <= Tsunami::Max_CPUs);
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if (ipintr) {
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for (int cpunum=0; cpunum < numcpus; cpunum++) {
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// Check each cpu bit
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uint64_t cpumask = ULL(1) << cpunum;
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if (ipintr & cpumask) {
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// Check if there is a pending ipi
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if (ipint & cpumask) {
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ipint &= ~cpumask;
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tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
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DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
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}
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else
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warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
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}
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}
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}
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else
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panic("Big IPI Clear, but not processors indicated\n");
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}
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void
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TsunamiCChip::clearITI(uint64_t itintr)
|
|
{
|
|
int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
|
|
assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (itintr) {
|
|
for (int i=0; i < numcpus; i++) {
|
|
uint64_t cpumask = ULL(1) << i;
|
|
if (itintr & cpumask & itint) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
|
|
itint &= ~cpumask;
|
|
DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big ITI Clear, but not processors indicated\n");
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::reqIPI(uint64_t ipreq)
|
|
{
|
|
int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
|
|
assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (ipreq) {
|
|
for (int cpunum=0; cpunum < numcpus; cpunum++) {
|
|
// Check each cpu bit
|
|
uint64_t cpumask = ULL(1) << cpunum;
|
|
if (ipreq & cpumask) {
|
|
// Check if there is already an ipi (bits 8:11)
|
|
if (!(ipint & cpumask)) {
|
|
ipint |= cpumask;
|
|
tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
|
|
DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
|
|
}
|
|
else
|
|
warn("post IPI for CPU=%d, but IPI already\n", cpunum);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big IPI Request, but not processors indicated\n");
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::postRTC()
|
|
{
|
|
int size = tsunami->intrctrl->cpu->system->threadContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
for (int i = 0; i < size; i++) {
|
|
uint64_t cpumask = ULL(1) << i;
|
|
if (!(cpumask & itint)) {
|
|
itint |= cpumask;
|
|
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
|
|
DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::postDRIR(uint32_t interrupt)
|
|
{
|
|
uint64_t bitvector = ULL(1) << interrupt;
|
|
uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
drir |= bitvector;
|
|
|
|
for(int i=0; i < size; i++) {
|
|
dir[i] = dim[i] & drir;
|
|
if (dim[i] & bitvector) {
|
|
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::clearDRIR(uint32_t interrupt)
|
|
{
|
|
uint64_t bitvector = ULL(1) << interrupt;
|
|
uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
if (drir & bitvector)
|
|
{
|
|
drir &= ~bitvector;
|
|
for(int i=0; i < size; i++) {
|
|
if (dir[i] & bitvector) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
|
|
}
|
|
dir[i] = dim[i] & drir;
|
|
}
|
|
}
|
|
else
|
|
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
SERIALIZE_SCALAR(ipint);
|
|
SERIALIZE_SCALAR(itint);
|
|
SERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_SCALAR(ipint);
|
|
UNSERIALIZE_SCALAR(itint);
|
|
UNSERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
Param<Addr> pio_addr;
|
|
Param<Tick> pio_latency;
|
|
SimObjectParam<Platform *> platform;
|
|
SimObjectParam<System *> system;
|
|
SimObjectParam<Tsunami *> tsunami;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
INIT_PARAM(pio_addr, "Device Address"),
|
|
INIT_PARAM(pio_latency, "Programmed IO latency"),
|
|
INIT_PARAM(platform, "platform"),
|
|
INIT_PARAM(system, "system object"),
|
|
INIT_PARAM(tsunami, "Tsunami")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
CREATE_SIM_OBJECT(TsunamiCChip)
|
|
{
|
|
TsunamiCChip::Params *p = new TsunamiCChip::Params;
|
|
p->name = getInstanceName();
|
|
p->pio_addr = pio_addr;
|
|
p->pio_delay = pio_latency;
|
|
p->platform = platform;
|
|
p->system = system;
|
|
p->tsunami = tsunami;
|
|
return new TsunamiCChip(p);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|