eb0e416998
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.
src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
Change ExecContext to ThreadContext.
--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
346 lines
11 KiB
C++
346 lines
11 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Ali Saidi
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* Steve Reinhardt
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* Erik Hallnor
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*/
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/** @file
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* Alpha Console Definition
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*/
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#include <cstddef>
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#include <string>
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#include "arch/alpha/system.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "dev/alpha_console.hh"
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#include "dev/platform.hh"
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#include "dev/simconsole.hh"
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#include "dev/simple_disk.hh"
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#include "mem/physical.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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using namespace std;
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using namespace AlphaISA;
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AlphaConsole::AlphaConsole(Params *p)
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: BasicPioDevice(p), disk(p->disk),
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console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
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{
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pioSize = sizeof(struct AlphaAccess);
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alphaAccess = new Access();
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alphaAccess->last_offset = pioSize - 1;
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alphaAccess->version = ALPHA_ACCESS_VERSION;
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alphaAccess->diskUnit = 1;
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alphaAccess->diskCount = 0;
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alphaAccess->diskPAddr = 0;
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alphaAccess->diskBlock = 0;
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alphaAccess->diskOperation = 0;
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alphaAccess->outputChar = 0;
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alphaAccess->inputChar = 0;
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bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
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}
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void
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AlphaConsole::startup()
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{
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system->setAlphaAccess(pioAddr);
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alphaAccess->numCPUs = system->getNumCPUs();
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alphaAccess->kernStart = system->getKernelStart();
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alphaAccess->kernEnd = system->getKernelEnd();
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alphaAccess->entryPoint = system->getKernelEntry();
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alphaAccess->mem_size = system->physmem->size();
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alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
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alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
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}
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Tick
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AlphaConsole::read(Packet *pkt)
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{
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/** XXX Do we want to push the addr munging to a bus brige or something? So
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* the device has it's physical address and then the bridge adds on whatever
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* machine dependent address swizzle is required?
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*/
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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pkt->allocate();
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switch (pkt->getSize())
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{
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case sizeof(uint32_t):
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switch (daddr)
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{
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case offsetof(AlphaAccess, last_offset):
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pkt->set(alphaAccess->last_offset);
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break;
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case offsetof(AlphaAccess, version):
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pkt->set(alphaAccess->version);
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break;
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case offsetof(AlphaAccess, numCPUs):
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pkt->set(alphaAccess->numCPUs);
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break;
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case offsetof(AlphaAccess, intrClockFrequency):
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pkt->set(alphaAccess->intrClockFrequency);
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break;
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default:
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/* Old console code read in everyting as a 32bit int
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* we now break that for better error checking.
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*/
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pkt->result = Packet::BadAddress;
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}
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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pkt->get<uint32_t>());
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break;
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case sizeof(uint64_t):
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switch (daddr)
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{
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case offsetof(AlphaAccess, inputChar):
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pkt->set(console->console_in());
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break;
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case offsetof(AlphaAccess, cpuClock):
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pkt->set(alphaAccess->cpuClock);
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break;
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case offsetof(AlphaAccess, mem_size):
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pkt->set(alphaAccess->mem_size);
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break;
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case offsetof(AlphaAccess, kernStart):
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pkt->set(alphaAccess->kernStart);
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break;
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case offsetof(AlphaAccess, kernEnd):
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pkt->set(alphaAccess->kernEnd);
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break;
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case offsetof(AlphaAccess, entryPoint):
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pkt->set(alphaAccess->entryPoint);
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break;
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case offsetof(AlphaAccess, diskUnit):
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pkt->set(alphaAccess->diskUnit);
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break;
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case offsetof(AlphaAccess, diskCount):
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pkt->set(alphaAccess->diskCount);
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break;
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case offsetof(AlphaAccess, diskPAddr):
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pkt->set(alphaAccess->diskPAddr);
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break;
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case offsetof(AlphaAccess, diskBlock):
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pkt->set(alphaAccess->diskBlock);
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break;
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case offsetof(AlphaAccess, diskOperation):
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pkt->set(alphaAccess->diskOperation);
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break;
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case offsetof(AlphaAccess, outputChar):
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pkt->set(alphaAccess->outputChar);
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break;
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default:
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int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
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sizeof(alphaAccess->cpuStack[0]);
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if (cpunum >= 0 && cpunum < 64)
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pkt->set(alphaAccess->cpuStack[cpunum]);
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else
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
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pkt->get<uint64_t>());
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break;
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default:
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pkt->result = Packet::BadAddress;
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}
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if (pkt->result == Packet::Unknown)
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pkt->result = Packet::Success;
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return pioDelay;
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}
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Tick
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AlphaConsole::write(Packet *pkt)
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{
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assert(pkt->result == Packet::Unknown);
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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uint64_t val = pkt->get<uint64_t>();
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assert(pkt->getSize() == sizeof(uint64_t));
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switch (daddr) {
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case offsetof(AlphaAccess, diskUnit):
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alphaAccess->diskUnit = val;
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break;
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case offsetof(AlphaAccess, diskCount):
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alphaAccess->diskCount = val;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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alphaAccess->diskPAddr = val;
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break;
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case offsetof(AlphaAccess, diskBlock):
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alphaAccess->diskBlock = val;
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break;
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case offsetof(AlphaAccess, diskOperation):
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if (val == 0x13)
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disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
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alphaAccess->diskCount);
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else
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panic("Invalid disk operation!");
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break;
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case offsetof(AlphaAccess, outputChar):
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console->out((char)(val & 0xff));
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break;
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default:
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int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
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sizeof(alphaAccess->cpuStack[0]);
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warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
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assert(val > 0 && "Must not access primary cpu");
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if (cpunum >= 0 && cpunum < 64)
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alphaAccess->cpuStack[cpunum] = val;
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else
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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pkt->result = Packet::Success;
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return pioDelay;
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}
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void
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AlphaConsole::Access::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(last_offset);
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SERIALIZE_SCALAR(version);
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SERIALIZE_SCALAR(numCPUs);
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SERIALIZE_SCALAR(mem_size);
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SERIALIZE_SCALAR(cpuClock);
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SERIALIZE_SCALAR(intrClockFrequency);
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SERIALIZE_SCALAR(kernStart);
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SERIALIZE_SCALAR(kernEnd);
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SERIALIZE_SCALAR(entryPoint);
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SERIALIZE_SCALAR(diskUnit);
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SERIALIZE_SCALAR(diskCount);
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SERIALIZE_SCALAR(diskPAddr);
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SERIALIZE_SCALAR(diskBlock);
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SERIALIZE_SCALAR(diskOperation);
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SERIALIZE_SCALAR(outputChar);
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SERIALIZE_SCALAR(inputChar);
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SERIALIZE_ARRAY(cpuStack,64);
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}
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void
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AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(last_offset);
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UNSERIALIZE_SCALAR(version);
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UNSERIALIZE_SCALAR(numCPUs);
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UNSERIALIZE_SCALAR(mem_size);
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UNSERIALIZE_SCALAR(cpuClock);
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UNSERIALIZE_SCALAR(intrClockFrequency);
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UNSERIALIZE_SCALAR(kernStart);
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UNSERIALIZE_SCALAR(kernEnd);
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UNSERIALIZE_SCALAR(entryPoint);
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UNSERIALIZE_SCALAR(diskUnit);
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UNSERIALIZE_SCALAR(diskCount);
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UNSERIALIZE_SCALAR(diskPAddr);
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UNSERIALIZE_SCALAR(diskBlock);
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UNSERIALIZE_SCALAR(diskOperation);
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UNSERIALIZE_SCALAR(outputChar);
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UNSERIALIZE_SCALAR(inputChar);
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UNSERIALIZE_ARRAY(cpuStack, 64);
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}
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void
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AlphaConsole::serialize(ostream &os)
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{
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alphaAccess->serialize(os);
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}
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void
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AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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alphaAccess->unserialize(cp, section);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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SimObjectParam<SimConsole *> sim_console;
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SimObjectParam<SimpleDisk *> disk;
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Param<Addr> pio_addr;
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SimObjectParam<AlphaSystem *> system;
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SimObjectParam<BaseCPU *> cpu;
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SimObjectParam<Platform *> platform;
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Param<Tick> pio_latency;
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END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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INIT_PARAM(sim_console, "The Simulator Console"),
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INIT_PARAM(disk, "Simple Disk"),
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INIT_PARAM(pio_addr, "Device Address"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu, "Processor"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
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END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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CREATE_SIM_OBJECT(AlphaConsole)
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{
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AlphaConsole::Params *p = new AlphaConsole::Params;
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p->name = getInstanceName();
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p->platform = platform;
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p->pio_addr = pio_addr;
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p->pio_delay = pio_latency;
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p->cons = sim_console;
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p->disk = disk;
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p->alpha_sys = system;
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p->system = system;
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p->cpu = cpu;
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return new AlphaConsole(p);
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}
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REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
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