gem5/src/arch
Gabe Black 82a228bd43 Decode: Make the Decoder class defined per ISA.
--HG--
rename : src/cpu/decode.cc => src/arch/generic/decoder.cc
rename : src/cpu/decode.hh => src/arch/generic/decoder.hh
2012-05-25 00:53:37 -07:00
..
alpha Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
arm Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
generic Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
mips Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
noisa cpu: add separate stats for insts/ops both globally and per cpu model 2012-02-12 16:07:39 -06:00
power Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
sparc Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
x86 Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
isa_parser.py ISA parser: Use '_' instead of '.' to delimit type modifiers on operands. 2011-09-26 23:48:54 -07:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00