gem5/tests/configs/o3-timing-ruby.py
Andreas Hansson 68fdccb30b ruby: Fix regressions and make Ruby configs Python packages
This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.

As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.
2016-10-13 03:17:19 -04:00

57 lines
2.4 KiB
Python

# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
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# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# Authors: Steve Reinhardt
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
cpu = DerivO3CPU(cpu_id=0)
system = System(cpu = cpu,
physmem = ruby_memory,
membus = SystemXBar(),
mem_mode = "timing",
clk_domain = SrcClockDomain(clock = '1GHz'))
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
# Connect the system port for loading of binaries etc
system.system_port = system.membus.slave
root = Root(full_system = False, system = system)