gem5/src/arch
Steve Reinhardt b0b1c0205c devices: make more classes derive from BasicPioDevice
A couple of devices that have single fixed memory mapped regions
were not derived from BasicPioDevice, when that's exactly
the functionality that BasicPioDevice provides.  This patch
gets rid of a little bit of redundant code by making those
devices actually do so.

Also fixed the weird case of X86ISA::Interrupts, where
the class already did derive from BasicPioDevice but
didn't actually use all the features it could have.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-07-11 21:56:24 -05:00
..
alpha sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
arm arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
generic arch: Fix broken M5VarArgsFault initialization 2013-01-07 13:05:38 -05:00
mips sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
noisa cpu: add separate stats for insts/ops both globally and per cpu model 2012-02-12 16:07:39 -06:00
power arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
sparc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
x86 devices: make more classes derive from BasicPioDevice 2013-07-11 21:56:24 -05:00
isa_parser.py O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript CPU: Merge the predecoder and decoder. 2012-05-26 13:44:46 -07:00