105 lines
3.7 KiB
C++
105 lines
3.7 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
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#define __CPU_OZONE_NULL_PREDICTOR_HH__
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#include "cpu/inst_seq.hh"
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#include "sim/host.hh"
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template <class Impl>
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class NullPredictor
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{
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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NullPredictor(Params *p) { }
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struct BPredInfo {
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BPredInfo()
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: PC(0), nextPC(0)
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{ }
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BPredInfo(const Addr &pc, const Addr &next_pc)
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: PC(pc), nextPC(next_pc)
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{ }
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Addr PC;
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Addr nextPC;
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};
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BPredInfo lookup(Addr &PC) { return BPredInfo(PC, PC+4); }
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void undo(BPredInfo &bp_info) { return; }
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/**
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* Predicts whether or not the instruction is a taken branch, and the
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* target of the branch if it is taken.
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* @param inst The branch instruction.
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* @param PC The predicted PC is passed back through this parameter.
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* @param tid The thread id.
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* @return Returns if the branch is taken or not.
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*/
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bool predict(DynInstPtr &inst, Addr &PC, unsigned tid)
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{ return false; }
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/**
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* Tells the branch predictor to commit any updates until the given
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* sequence number.
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* @param done_sn The sequence number to commit any older updates up until.
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* @param tid The thread id.
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*/
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void update(const InstSeqNum &done_sn, unsigned tid) { }
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/**
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* Squashes all outstanding updates until a given sequence number.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, unsigned tid) { }
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/**
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* Squashes all outstanding updates until a given sequence number, and
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* corrects that sn's update with the proper address and taken/not taken.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param corr_target The correct branch target.
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* @param actually_taken The correct branch direction.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
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bool actually_taken, unsigned tid)
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{ }
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};
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#endif // __CPU_OZONE_NULL_PREDICTOR_HH__
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