cdacbe734a
This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path. |
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.. | ||
atomic.cc | ||
atomic.hh | ||
AtomicSimpleCPU.py | ||
base.cc | ||
base.hh | ||
BaseSimpleCPU.py | ||
SConscript | ||
SConsopts | ||
timing.cc | ||
timing.hh | ||
TimingSimpleCPU.py |