gem5/src/cpu/simple
Ali Saidi cdacbe734a ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.

On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.
2010-11-08 13:58:22 -06:00
..
atomic.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
atomic.hh CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
AtomicSimpleCPU.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00
base.cc ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. 2010-11-08 13:58:22 -06:00
base.hh ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. 2010-11-08 13:58:22 -06:00
BaseSimpleCPU.py params: Convert the CPU objects to use the auto generated param structs. 2008-08-11 12:22:16 -07:00
SConscript params: Convert the CPU objects to use the auto generated param structs. 2008-08-11 12:22:16 -07:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
timing.cc ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. 2010-11-08 13:58:22 -06:00
timing.hh CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
TimingSimpleCPU.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00