0b2deb2a88
arch/alpha/arguments.cc:
There will not be a phys mem ptr in the XC in the newmem. This read will have to go through something else.
arch/alpha/ev5.cc:
Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used. Also this messed up the ability to specify which CPU models are being built.
cpu/exec_context.hh:
Remove getPhysMemPtr() function.
cpu/exetrace.cc:
Include sim/system.hh, and sort the includes.
cpu/simple/cpu.cc:
Fixes for full system compilation.
kern/system_events.cc:
Remove include of encumbered FullCPU. The branch prediction will need to be fixed up in a more generic way in the future.
--HG--
extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c
91 lines
3 KiB
C++
91 lines
3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "kern/kernel_stats.hh"
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#include "kern/system_events.hh"
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#include "sim/system.hh"
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using namespace TheISA;
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void
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SkipFuncEvent::process(ExecContext *xc)
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{
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Addr newpc = xc->readIntReg(ReturnAddressReg);
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DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
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xc->readPC(), newpc);
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xc->setPC(newpc);
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xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst));
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/*
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BranchPred *bp = xc->getCpuPtr()->getBranchPred();
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if (bp != NULL) {
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bp->popRAS(xc->getThreadNum());
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}
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*/
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}
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FnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr,
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Stats::MainBin *bin)
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: PCEvent(q, desc, addr), _name(desc), mybin(bin)
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{
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}
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void
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FnEvent::process(ExecContext *xc)
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{
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if (xc->misspeculating())
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return;
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xc->getSystemPtr()->kernelBinning->call(xc, mybin);
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}
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void
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IdleStartEvent::process(ExecContext *xc)
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{
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xc->getCpuPtr()->kernelStats->setIdleProcess(
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xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc);
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remove();
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}
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void
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InterruptStartEvent::process(ExecContext *xc)
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{
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xc->getCpuPtr()->kernelStats->mode(Kernel::interrupt, xc);
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}
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void
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InterruptEndEvent::process(ExecContext *xc)
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{
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// We go back to kernel, if we are user, inside the rti
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// pal code we will get switched to user because of the ICM write
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xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
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}
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