Dam Sunwoo 2c1e344313 cpu: generate SimPoint basic block vector profiles ... This patch is based on http://reviews.m5sim.org/r/1474/ originally written by Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout folder) based on start and end addresses of basic blocks. Some comments to the original patch are addressed and hooks are added to create and resume from checkpoints based on instruction counts dictated by external SimPoint analysis tools. SimPoint creation/resuming options will be implemented as a separate patch.		2013-04-22 13:20:31 -04:00
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fs.py	options: add command line option for dtb file	2013-02-15 18:48:59 -05:00
memtest.py	Configs: Fix memtest cache latency to match new parameters	2012-09-27 08:59:25 -04:00
ruby_direct_test.py	ruby: modify the directed tester to read/write streams	2012-12-11 10:05:55 -06:00
ruby_fs.py	ruby: remove the functional copy of memory in se mode	2013-03-06 21:53:57 -06:00
ruby_mem_test.py	ruby: improved support for functional accesses	2012-10-15 17:51:57 -05:00
ruby_network_test.py	ruby: changes how Topologies are created	2012-07-10 22:51:53 -07:00
ruby_random_test.py	ruby: remove the cpu assumptions for the random tester	2012-07-10 22:51:54 -07:00
se.py	cpu: generate SimPoint basic block vector profiles	2013-04-22 13:20:31 -04:00