736 lines
31 KiB
Text
736 lines
31 KiB
Text
Real time: Mar/28/2013 10:19:36
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 824
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Elapsed_time_in_minutes: 13.7333
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Elapsed_time_in_hours: 0.228889
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Elapsed_time_in_days: 0.00953704
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Virtual_time_in_seconds: 785.96
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Virtual_time_in_minutes: 13.0993
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Virtual_time_in_hours: 0.218322
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Virtual_time_in_days: 0.00909676
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Ruby_current_time: 10416271238
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Ruby_start_time: 0
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Ruby_cycles: 10416271238
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mbytes_resident: 597.965
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mbytes_total: 848.508
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resident_ratio: 0.704734
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ruby_cycles_executed: [ 10416271239 10416271239 ]
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Busy Controller Counts:
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L1Cache-0:0 L1Cache-1:0
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L2Cache-0:0
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Directory-0:0
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DMA-0:0
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Busy Bank Count:0
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sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151895075 average: 1.00011 | standard deviation: 0.0104983 | 0 151878333 16742 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ]
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miss_latency_NULL: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_LD_NULL: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | standard deviation: 1.42425 | 9251200 1053 635 975 1612868 1042 121 110 109 275 4 9 9 51 0 0 1 0 0 1 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 19 count: 6100210 average: 1.0435 | standard deviation: 1.75778 | 4509207 549 222 262 1588385 908 120 110 101 271 4 9 9 51 0 0 1 0 0 1 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4687708 average: 0.0215679 | standard deviation: 0.291665 | 4661845 408 333 614 24389 107 1 0 8 3 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 80545 average: 0.0133217 | standard deviation: 0.21003 | 80148 96 80 99 94 27 0 0 0 1 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 784
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system_time: 1
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page_reclaims: 148403
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page_faults: 35
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swaps: 0
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block_inputs: 20600
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block_outputs: 736
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Network Stats
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-------------
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total_msg_count_Control: 8498316 67986528
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total_msg_count_Request_Control: 239871 1918968
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total_msg_count_Response_Data: 8796423 633342456
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total_msg_count_Response_Control: 10879743 87037944
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total_msg_count_Writeback_Data: 4769004 343368288
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total_msg_count_Writeback_Control: 289518 2316144
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total_msgs: 33472875 total_bytes: 1135970328
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.0315382
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links_utilized_percent_switch_0_link_0: 0.037253 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.0258234 bw: 16000 base_latency: 1
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outgoing_messages_switch_0_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 817583 6540664 [ 817583 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Response_Data: 39381 2835432 [ 0 39381 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Response_Control: 495523 3964184 [ 0 15983 479540 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 408673 29424456 [ 408575 98 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Control: 34072 272576 [ 34072 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.0764968
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links_utilized_percent_switch_1_link_0: 0.0852244 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.0677692 bw: 16000 base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Control: 1837549 14700392 [ 1837549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 32554 2343888 [ 0 32554 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Control: 1296124 10368992 [ 0 16536 1279588 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Data: 1180995 85031640 [ 1180869 126 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 62434 499472 [ 62434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 0.112511
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links_utilized_percent_switch_2_link_0: 0.0996306 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 0.125392 bw: 16000 base_latency: 1
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outgoing_messages_switch_2_link_0_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Request_Control: 78781 630248 [ 78781 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Response_Data: 2682566 193144752 [ 0 2682566 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Response_Control: 1722824 13782592 [ 0 1722824 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_3_inlinks: 2
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switch_3_outlinks: 2
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links_utilized_percent_switch_3: 0.00665498
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links_utilized_percent_switch_3_link_0: 0.00509748 bw: 16000 base_latency: 1
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links_utilized_percent_switch_3_link_1: 0.00821249 bw: 16000 base_latency: 1
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outgoing_messages_switch_3_link_0_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Response_Data: 177640 12790080 [ 0 177640 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Response_Control: 112110 896880 [ 0 112110 0 0 0 0 0 0 0 0 ] base_latency: 1
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switch_4_inlinks: 2
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switch_4_outlinks: 2
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links_utilized_percent_switch_4: 0
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links_utilized_percent_switch_4_link_0: 0 bw: 16000 base_latency: 1
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links_utilized_percent_switch_4_link_1: 0 bw: 16000 base_latency: 1
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switch_5_inlinks: 5
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switch_5_outlinks: 5
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links_utilized_percent_switch_5: 0.0454411
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links_utilized_percent_switch_5_link_0: 0.037253 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_1: 0.0852244 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_2: 0.0996306 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_3: 0.00509748 bw: 16000 base_latency: 1
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links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
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outgoing_messages_switch_5_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_1_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_1_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_1_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_2_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_3_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_3_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_5_link_3_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1
|
|
|
|
Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 313126
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 313126
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
|
|
|
system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 313126 100%
|
|
|
|
Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 504457
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 504457
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.7331%
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.2669%
|
|
|
|
system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 504457 100%
|
|
|
|
--- L1Cache ---
|
|
- Event Counts -
|
|
Load [6004899 8869162 ] 14874061
|
|
Ifetch [67402410 58977750 ] 126380160
|
|
Store [5078812 5562047 ] 10640859
|
|
Inv [16081 16662 ] 32743
|
|
L1_Replacement [790678 1810849 ] 2601527
|
|
Fwd_GETX [12181 11488 ] 23669
|
|
Fwd_GETS [13596 10533 ] 24129
|
|
Fwd_GET_INSTR [4 0 ] 4
|
|
Data [367 1125 ] 1492
|
|
Data_Exclusive [240655 1040298 ] 1280953
|
|
DataS_fromL1 [10533 13600 ] 24133
|
|
Data_all_Acks [554260 773007 ] 1327267
|
|
Ack [11768 9519 ] 21287
|
|
Ack_all [12135 10644 ] 22779
|
|
WB_Ack [442647 1243303 ] 1685950
|
|
PF_Load [0 0 ] 0
|
|
PF_Ifetch [0 0 ] 0
|
|
PF_Store [0 0 ] 0
|
|
|
|
- Transitions -
|
|
NP Load [267792 1102795 ] 1370587
|
|
NP Ifetch [313000 498627 ] 811627
|
|
NP Store [210910 210451 ] 421361
|
|
NP Inv [5429 3933 ] 9362
|
|
NP L1_Replacement [0 0 ] 0
|
|
NP PF_Load [0 0 ] 0
|
|
NP PF_Ifetch [0 0 ] 0
|
|
NP PF_Store [0 0 ] 0
|
|
|
|
I Load [8313 10000 ] 18313
|
|
I Ifetch [126 437 ] 563
|
|
I Store [5674 5720 ] 11394
|
|
I Inv [0 0 ] 0
|
|
I L1_Replacement [8682 8060 ] 16742
|
|
I PF_Load [0 0 ] 0
|
|
I PF_Ifetch [0 0 ] 0
|
|
I PF_Store [0 0 ] 0
|
|
|
|
S Load [551889 484566 ] 1036455
|
|
S Ifetch [67089280 58478684 ] 125567964
|
|
S Store [11768 9519 ] 21287
|
|
S Inv [10451 12551 ] 23002
|
|
S L1_Replacement [339349 559486 ] 898835
|
|
S PF_Load [0 0 ] 0
|
|
S PF_Store [0 0 ] 0
|
|
|
|
E Load [1058703 2799902 ] 3858605
|
|
E Ifetch [0 0 ] 0
|
|
E Store [78784 87850 ] 166634
|
|
E Inv [103 52 ] 155
|
|
E L1_Replacement [160570 950900 ] 1111470
|
|
E Fwd_GETX [228 182 ] 410
|
|
E Fwd_GETS [848 1108 ] 1956
|
|
E Fwd_GET_INSTR [0 0 ] 0
|
|
E PF_Load [0 0 ] 0
|
|
E PF_Store [0 0 ] 0
|
|
|
|
M Load [4118202 4471899 ] 8590101
|
|
M Ifetch [0 0 ] 0
|
|
M Store [4771676 5248507 ] 10020183
|
|
M Inv [98 126 ] 224
|
|
M L1_Replacement [282077 292403 ] 574480
|
|
M Fwd_GETX [11953 11306 ] 23259
|
|
M Fwd_GETS [12747 9423 ] 22170
|
|
M Fwd_GET_INSTR [4 0 ] 4
|
|
M PF_Load [0 0 ] 0
|
|
M PF_Store [0 0 ] 0
|
|
|
|
IS Load [0 0 ] 0
|
|
IS Ifetch [0 0 ] 0
|
|
IS Store [0 0 ] 0
|
|
IS Inv [0 0 ] 0
|
|
IS L1_Replacement [0 0 ] 0
|
|
IS Data_Exclusive [240655 1040298 ] 1280953
|
|
IS DataS_fromL1 [10533 13600 ] 24133
|
|
IS Data_all_Acks [338043 557961 ] 896004
|
|
IS PF_Load [0 0 ] 0
|
|
IS PF_Store [0 0 ] 0
|
|
|
|
IM Load [0 0 ] 0
|
|
IM Ifetch [0 0 ] 0
|
|
IM Store [0 0 ] 0
|
|
IM Inv [0 0 ] 0
|
|
IM L1_Replacement [0 0 ] 0
|
|
IM Data [367 1125 ] 1492
|
|
IM Data_all_Acks [216217 215046 ] 431263
|
|
IM Ack [0 0 ] 0
|
|
IM PF_Load [0 0 ] 0
|
|
IM PF_Store [0 0 ] 0
|
|
|
|
SM Load [0 0 ] 0
|
|
SM Ifetch [0 0 ] 0
|
|
SM Store [0 0 ] 0
|
|
SM Inv [0 0 ] 0
|
|
SM L1_Replacement [0 0 ] 0
|
|
SM Ack [11768 9519 ] 21287
|
|
SM Ack_all [12135 10644 ] 22779
|
|
SM PF_Load [0 0 ] 0
|
|
SM PF_Store [0 0 ] 0
|
|
|
|
IS_I Load [0 0 ] 0
|
|
IS_I Ifetch [0 0 ] 0
|
|
IS_I Store [0 0 ] 0
|
|
IS_I Inv [0 0 ] 0
|
|
IS_I L1_Replacement [0 0 ] 0
|
|
IS_I Data_Exclusive [0 0 ] 0
|
|
IS_I DataS_fromL1 [0 0 ] 0
|
|
IS_I Data_all_Acks [0 0 ] 0
|
|
IS_I PF_Load [0 0 ] 0
|
|
IS_I PF_Store [0 0 ] 0
|
|
|
|
M_I Load [0 0 ] 0
|
|
M_I Ifetch [4 2 ] 6
|
|
M_I Store [0 0 ] 0
|
|
M_I Inv [0 0 ] 0
|
|
M_I L1_Replacement [0 0 ] 0
|
|
M_I Fwd_GETX [0 0 ] 0
|
|
M_I Fwd_GETS [1 2 ] 3
|
|
M_I Fwd_GET_INSTR [0 0 ] 0
|
|
M_I WB_Ack [442646 1243301 ] 1685947
|
|
M_I PF_Load [0 0 ] 0
|
|
M_I PF_Store [0 0 ] 0
|
|
|
|
SINK_WB_ACK Load [0 0 ] 0
|
|
SINK_WB_ACK Ifetch [0 0 ] 0
|
|
SINK_WB_ACK Store [0 0 ] 0
|
|
SINK_WB_ACK Inv [0 0 ] 0
|
|
SINK_WB_ACK L1_Replacement [0 0 ] 0
|
|
SINK_WB_ACK WB_Ack [1 2 ] 3
|
|
SINK_WB_ACK PF_Load [0 0 ] 0
|
|
SINK_WB_ACK PF_Store [0 0 ] 0
|
|
|
|
PF_IS Load [0 0 ] 0
|
|
PF_IS Ifetch [0 0 ] 0
|
|
PF_IS Store [0 0 ] 0
|
|
PF_IS Inv [0 0 ] 0
|
|
PF_IS L1_Replacement [0 0 ] 0
|
|
PF_IS Data_Exclusive [0 0 ] 0
|
|
PF_IS DataS_fromL1 [0 0 ] 0
|
|
PF_IS Data_all_Acks [0 0 ] 0
|
|
PF_IS PF_Load [0 0 ] 0
|
|
PF_IS PF_Store [0 0 ] 0
|
|
|
|
PF_IM Load [0 0 ] 0
|
|
PF_IM Ifetch [0 0 ] 0
|
|
PF_IM Store [0 0 ] 0
|
|
PF_IM Inv [0 0 ] 0
|
|
PF_IM L1_Replacement [0 0 ] 0
|
|
PF_IM Data [0 0 ] 0
|
|
PF_IM Data_all_Acks [0 0 ] 0
|
|
PF_IM Ack [0 0 ] 0
|
|
PF_IM PF_Load [0 0 ] 0
|
|
PF_IM PF_Store [0 0 ] 0
|
|
|
|
PF_SM Load [0 0 ] 0
|
|
PF_SM Ifetch [0 0 ] 0
|
|
PF_SM Store [0 0 ] 0
|
|
PF_SM Inv [0 0 ] 0
|
|
PF_SM L1_Replacement [0 0 ] 0
|
|
PF_SM Ack [0 0 ] 0
|
|
PF_SM Ack_all [0 0 ] 0
|
|
|
|
PF_IS_I Load [0 0 ] 0
|
|
PF_IS_I Store [0 0 ] 0
|
|
PF_IS_I Inv [0 0 ] 0
|
|
PF_IS_I L1_Replacement [0 0 ] 0
|
|
PF_IS_I Data_Exclusive [0 0 ] 0
|
|
PF_IS_I DataS_fromL1 [0 0 ] 0
|
|
PF_IS_I Data_all_Acks [0 0 ] 0
|
|
|
|
Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 499064
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 499064
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
|
|
|
|
system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 499064 100%
|
|
|
|
Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1338485
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1338485
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.1384%
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.8616%
|
|
|
|
system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1338485 100%
|
|
|
|
Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 225442
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 225442
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
|
system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
|
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 25.7405%
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.27238%
|
|
system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.9871%
|
|
|
|
system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 225442 100%
|
|
|
|
--- L2Cache ---
|
|
- Event Counts -
|
|
L1_GET_INSTR [812190 ] 812190
|
|
L1_GETS [1389132 ] 1389132
|
|
L1_GETX [432758 ] 432758
|
|
L1_UPGRADE [21287 ] 21287
|
|
L1_PUTX [1685953 ] 1685953
|
|
L1_PUTX_old [0 ] 0
|
|
Fwd_L1_GETX [0 ] 0
|
|
Fwd_L1_GETS [0 ] 0
|
|
Fwd_L1_GET_INSTR [0 ] 0
|
|
L2_Replacement [96407 ] 96407
|
|
L2_Replacement_clean [15703 ] 15703
|
|
Mem_Data [177640 ] 177640
|
|
Mem_Ack [112110 ] 112110
|
|
WB_Data [23855 ] 23855
|
|
WB_Data_clean [502 ] 502
|
|
Ack [1764 ] 1764
|
|
Ack_all [7976 ] 7976
|
|
Unblock [24133 ] 24133
|
|
Unblock_Cancel [0 ] 0
|
|
Exclusive_Unblock [1734995 ] 1734995
|
|
MEM_Inv [0 ] 0
|
|
|
|
- Transitions -
|
|
NP L1_GET_INSTR [16391 ] 16391
|
|
NP L1_GETS [33901 ] 33901
|
|
NP L1_GETX [127348 ] 127348
|
|
NP L1_PUTX [0 ] 0
|
|
NP L1_PUTX_old [0 ] 0
|
|
|
|
SS L1_GET_INSTR [795630 ] 795630
|
|
SS L1_GETS [83818 ] 83818
|
|
SS L1_GETX [1691 ] 1691
|
|
SS L1_UPGRADE [21287 ] 21287
|
|
SS L1_PUTX [3 ] 3
|
|
SS L1_PUTX_old [0 ] 0
|
|
SS L2_Replacement [258 ] 258
|
|
SS L2_Replacement_clean [7563 ] 7563
|
|
SS MEM_Inv [0 ] 0
|
|
|
|
M L1_GET_INSTR [165 ] 165
|
|
M L1_GETS [1247052 ] 1247052
|
|
M L1_GETX [280047 ] 280047
|
|
M L1_PUTX [0 ] 0
|
|
M L1_PUTX_old [0 ] 0
|
|
M L2_Replacement [95992 ] 95992
|
|
M L2_Replacement_clean [7918 ] 7918
|
|
M MEM_Inv [0 ] 0
|
|
|
|
MT L1_GET_INSTR [4 ] 4
|
|
MT L1_GETS [24129 ] 24129
|
|
MT L1_GETX [23669 ] 23669
|
|
MT L1_PUTX [1685947 ] 1685947
|
|
MT L1_PUTX_old [0 ] 0
|
|
MT L2_Replacement [157 ] 157
|
|
MT L2_Replacement_clean [222 ] 222
|
|
MT MEM_Inv [0 ] 0
|
|
|
|
M_I L1_GET_INSTR [0 ] 0
|
|
M_I L1_GETS [0 ] 0
|
|
M_I L1_GETX [0 ] 0
|
|
M_I L1_UPGRADE [0 ] 0
|
|
M_I L1_PUTX [0 ] 0
|
|
M_I L1_PUTX_old [0 ] 0
|
|
M_I Mem_Ack [112110 ] 112110
|
|
M_I MEM_Inv [0 ] 0
|
|
|
|
MT_I L1_GET_INSTR [0 ] 0
|
|
MT_I L1_GETS [0 ] 0
|
|
MT_I L1_GETX [0 ] 0
|
|
MT_I L1_UPGRADE [0 ] 0
|
|
MT_I L1_PUTX [0 ] 0
|
|
MT_I L1_PUTX_old [0 ] 0
|
|
MT_I WB_Data [108 ] 108
|
|
MT_I WB_Data_clean [0 ] 0
|
|
MT_I Ack_all [49 ] 49
|
|
MT_I MEM_Inv [0 ] 0
|
|
|
|
MCT_I L1_GET_INSTR [0 ] 0
|
|
MCT_I L1_GETS [0 ] 0
|
|
MCT_I L1_GETX [0 ] 0
|
|
MCT_I L1_UPGRADE [0 ] 0
|
|
MCT_I L1_PUTX [0 ] 0
|
|
MCT_I L1_PUTX_old [0 ] 0
|
|
MCT_I WB_Data [116 ] 116
|
|
MCT_I WB_Data_clean [0 ] 0
|
|
MCT_I Ack_all [106 ] 106
|
|
|
|
I_I L1_GET_INSTR [0 ] 0
|
|
I_I L1_GETS [0 ] 0
|
|
I_I L1_GETX [0 ] 0
|
|
I_I L1_UPGRADE [0 ] 0
|
|
I_I L1_PUTX [0 ] 0
|
|
I_I L1_PUTX_old [0 ] 0
|
|
I_I Ack [1506 ] 1506
|
|
I_I Ack_all [7563 ] 7563
|
|
|
|
S_I L1_GET_INSTR [0 ] 0
|
|
S_I L1_GETS [0 ] 0
|
|
S_I L1_GETX [0 ] 0
|
|
S_I L1_UPGRADE [0 ] 0
|
|
S_I L1_PUTX [0 ] 0
|
|
S_I L1_PUTX_old [0 ] 0
|
|
S_I Ack [258 ] 258
|
|
S_I Ack_all [258 ] 258
|
|
S_I MEM_Inv [0 ] 0
|
|
|
|
ISS L1_GET_INSTR [0 ] 0
|
|
ISS L1_GETS [0 ] 0
|
|
ISS L1_GETX [0 ] 0
|
|
ISS L1_PUTX [0 ] 0
|
|
ISS L1_PUTX_old [0 ] 0
|
|
ISS L2_Replacement [0 ] 0
|
|
ISS L2_Replacement_clean [0 ] 0
|
|
ISS Mem_Data [33901 ] 33901
|
|
ISS MEM_Inv [0 ] 0
|
|
|
|
IS L1_GET_INSTR [0 ] 0
|
|
IS L1_GETS [0 ] 0
|
|
IS L1_GETX [0 ] 0
|
|
IS L1_PUTX [0 ] 0
|
|
IS L1_PUTX_old [0 ] 0
|
|
IS L2_Replacement [0 ] 0
|
|
IS L2_Replacement_clean [0 ] 0
|
|
IS Mem_Data [16391 ] 16391
|
|
IS MEM_Inv [0 ] 0
|
|
|
|
IM L1_GET_INSTR [0 ] 0
|
|
IM L1_GETS [0 ] 0
|
|
IM L1_GETX [0 ] 0
|
|
IM L1_PUTX [0 ] 0
|
|
IM L1_PUTX_old [0 ] 0
|
|
IM L2_Replacement [0 ] 0
|
|
IM L2_Replacement_clean [0 ] 0
|
|
IM Mem_Data [127348 ] 127348
|
|
IM MEM_Inv [0 ] 0
|
|
|
|
SS_MB L1_GET_INSTR [0 ] 0
|
|
SS_MB L1_GETS [186 ] 186
|
|
SS_MB L1_GETX [1 ] 1
|
|
SS_MB L1_UPGRADE [0 ] 0
|
|
SS_MB L1_PUTX [0 ] 0
|
|
SS_MB L1_PUTX_old [0 ] 0
|
|
SS_MB L2_Replacement [0 ] 0
|
|
SS_MB L2_Replacement_clean [0 ] 0
|
|
SS_MB Unblock_Cancel [0 ] 0
|
|
SS_MB Exclusive_Unblock [22978 ] 22978
|
|
SS_MB MEM_Inv [0 ] 0
|
|
|
|
MT_MB L1_GET_INSTR [0 ] 0
|
|
MT_MB L1_GETS [46 ] 46
|
|
MT_MB L1_GETX [2 ] 2
|
|
MT_MB L1_UPGRADE [0 ] 0
|
|
MT_MB L1_PUTX [0 ] 0
|
|
MT_MB L1_PUTX_old [0 ] 0
|
|
MT_MB L2_Replacement [0 ] 0
|
|
MT_MB L2_Replacement_clean [0 ] 0
|
|
MT_MB Unblock_Cancel [0 ] 0
|
|
MT_MB Exclusive_Unblock [1712017 ] 1712017
|
|
MT_MB MEM_Inv [0 ] 0
|
|
|
|
M_MB L1_GET_INSTR [0 ] 0
|
|
M_MB L1_GETS [0 ] 0
|
|
M_MB L1_GETX [0 ] 0
|
|
M_MB L1_UPGRADE [0 ] 0
|
|
M_MB L1_PUTX [0 ] 0
|
|
M_MB L1_PUTX_old [0 ] 0
|
|
M_MB L2_Replacement [0 ] 0
|
|
M_MB L2_Replacement_clean [0 ] 0
|
|
M_MB Exclusive_Unblock [0 ] 0
|
|
M_MB MEM_Inv [0 ] 0
|
|
|
|
MT_IIB L1_GET_INSTR [0 ] 0
|
|
MT_IIB L1_GETS [0 ] 0
|
|
MT_IIB L1_GETX [0 ] 0
|
|
MT_IIB L1_UPGRADE [0 ] 0
|
|
MT_IIB L1_PUTX [3 ] 3
|
|
MT_IIB L1_PUTX_old [0 ] 0
|
|
MT_IIB L2_Replacement [0 ] 0
|
|
MT_IIB L2_Replacement_clean [0 ] 0
|
|
MT_IIB WB_Data [23620 ] 23620
|
|
MT_IIB WB_Data_clean [502 ] 502
|
|
MT_IIB Unblock [11 ] 11
|
|
MT_IIB MEM_Inv [0 ] 0
|
|
|
|
MT_IB L1_GET_INSTR [0 ] 0
|
|
MT_IB L1_GETS [0 ] 0
|
|
MT_IB L1_GETX [0 ] 0
|
|
MT_IB L1_UPGRADE [0 ] 0
|
|
MT_IB L1_PUTX [0 ] 0
|
|
MT_IB L1_PUTX_old [0 ] 0
|
|
MT_IB L2_Replacement [0 ] 0
|
|
MT_IB L2_Replacement_clean [0 ] 0
|
|
MT_IB WB_Data [11 ] 11
|
|
MT_IB WB_Data_clean [0 ] 0
|
|
MT_IB Unblock_Cancel [0 ] 0
|
|
MT_IB MEM_Inv [0 ] 0
|
|
|
|
MT_SB L1_GET_INSTR [0 ] 0
|
|
MT_SB L1_GETS [0 ] 0
|
|
MT_SB L1_GETX [0 ] 0
|
|
MT_SB L1_UPGRADE [0 ] 0
|
|
MT_SB L1_PUTX [0 ] 0
|
|
MT_SB L1_PUTX_old [0 ] 0
|
|
MT_SB L2_Replacement [0 ] 0
|
|
MT_SB L2_Replacement_clean [0 ] 0
|
|
MT_SB Unblock [24122 ] 24122
|
|
MT_SB MEM_Inv [0 ] 0
|
|
|
|
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
|
memory_total_requests: 274163
|
|
memory_reads: 177640
|
|
memory_writes: 96523
|
|
memory_refreshes: 588410
|
|
memory_total_request_delays: 1038324
|
|
memory_delays_per_request: 3.78725
|
|
memory_delays_in_input_queue: 39505
|
|
memory_delays_behind_head_of_bank_queue: 7889
|
|
memory_delays_stalled_at_head_of_bank_queue: 990930
|
|
memory_stalls_for_bank_busy: 981321
|
|
memory_stalls_for_random_busy: 0
|
|
memory_stalls_for_anti_starvation: 0
|
|
memory_stalls_for_arbitration: 2239
|
|
memory_stalls_for_bus: 7329
|
|
memory_stalls_for_tfaw: 0
|
|
memory_stalls_for_read_write_turnaround: 29
|
|
memory_stalls_for_read_read_turnaround: 12
|
|
accesses_per_bank: 9082 9112 8244 8400 9230 8573 8966 8230 8398 8230 8230 8246 8347 8114 8111 7298 8351 8467 8382 8429 8595 8485 8298 8250 8587 8384 8675 9378 9287 9169 10231 8384
|
|
|
|
--- Directory ---
|
|
- Event Counts -
|
|
Fetch [177640 ] 177640
|
|
Data [96523 ] 96523
|
|
Memory_Data [177640 ] 177640
|
|
Memory_Ack [96523 ] 96523
|
|
DMA_READ [0 ] 0
|
|
DMA_WRITE [0 ] 0
|
|
CleanReplacement [15587 ] 15587
|
|
|
|
- Transitions -
|
|
I Fetch [177640 ] 177640
|
|
I DMA_READ [0 ] 0
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
ID Fetch [0 ] 0
|
|
ID Data [0 ] 0
|
|
ID Memory_Data [0 ] 0
|
|
ID DMA_READ [0 ] 0
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
ID_W Fetch [0 ] 0
|
|
ID_W Data [0 ] 0
|
|
ID_W Memory_Ack [0 ] 0
|
|
ID_W DMA_READ [0 ] 0
|
|
ID_W DMA_WRITE [0 ] 0
|
|
|
|
M Data [96523 ] 96523
|
|
M DMA_READ [0 ] 0
|
|
M DMA_WRITE [0 ] 0
|
|
M CleanReplacement [15587 ] 15587
|
|
|
|
IM Fetch [0 ] 0
|
|
IM Data [0 ] 0
|
|
IM Memory_Data [177640 ] 177640
|
|
IM DMA_READ [0 ] 0
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
MI Fetch [0 ] 0
|
|
MI Data [0 ] 0
|
|
MI Memory_Ack [96523 ] 96523
|
|
MI DMA_READ [0 ] 0
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
M_DRD Data [0 ] 0
|
|
M_DRD DMA_READ [0 ] 0
|
|
M_DRD DMA_WRITE [0 ] 0
|
|
|
|
M_DRDI Fetch [0 ] 0
|
|
M_DRDI Data [0 ] 0
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
M_DRDI DMA_READ [0 ] 0
|
|
M_DRDI DMA_WRITE [0 ] 0
|
|
|
|
M_DWR Data [0 ] 0
|
|
M_DWR DMA_READ [0 ] 0
|
|
M_DWR DMA_WRITE [0 ] 0
|
|
|
|
M_DWRI Fetch [0 ] 0
|
|
M_DWRI Data [0 ] 0
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
M_DWRI DMA_READ [0 ] 0
|
|
M_DWRI DMA_WRITE [0 ] 0
|
|
|
|
--- DMA ---
|
|
- Event Counts -
|
|
ReadRequest [0 ] 0
|
|
WriteRequest [0 ] 0
|
|
Data [0 ] 0
|
|
Ack [0 ] 0
|
|
|
|
- Transitions -
|
|
READY ReadRequest [0 ] 0
|
|
READY WriteRequest [0 ] 0
|
|
|
|
BUSY_RD Data [0 ] 0
|
|
|
|
BUSY_WR Ack [0 ] 0
|
|
|