25a358983a
Add support for generic visitors for stats and use them to implement independent output functions. Support for mysql output and some initial code for hacking on mysql output with python arch/alpha/pseudo_inst.cc: base/hybrid_pred.cc: base/hybrid_pred.hh: base/sat_counter.cc: base/sat_counter.hh: cpu/simple_cpu/simple_cpu.cc: kern/tru64/tru64_events.cc: sim/main.cc: sim/process.cc: sim/process.hh: sim/sim_events.cc: sim/sim_object.cc: sim/system.hh: update for changes in stats package base/statistics.cc: move the python output code to base/stats/puthon.(cc|hh) and reimplement it as a visitor. move the text output code to base/stats/text.(cc|hh) and reimplement it as a visitor. move the database stuff into base/stats/statdb.(cc|hh) and get rid of the class. Put everything as globals in the Statistics::Database namespace. allocate unique ids for all stats. directly implement the check routine and get rid of the various dumping routines since they're now in separate files. make sure that no two stats have the same name clean up some loops base/statistics.hh: major changes to the statistics package again lots of code was factored out of statistics.hh into several separate files in base/stats/ (this will continue) There are now two Stat package types Result and Counter that are specified to allow the user to keep the counted type separate from the result type. They are currently both doubles but that's an experiment. There is no more per stat ability to set the type. Statistics::Counter is not the same as Counter! Implement a visitor for statistics output so that new output types can be implemented independently from the stats package itself. Add a unique id to each stat so that it can be used to keep track of stats more simply. This number can also be used in debugging problems with stats. Tweak the bucket size stuff a bit to make it work better. fixed VectorDist size bug cpu/memtest/memtest.cc: Fix up for changes in stats package Don't use value() since it doesn't work with binning. If you want a number as a stat, and to use it in the program itself, you really want two separate variables, one that's a stat, and one that's not. cpu/memtest/memtest.hh: Fix up for changes in stats package test/Makefile: Try to build stuff now that directories matter test/stattest.cc: test all new output types choose which one with command line options --HG-- extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
860 lines
22 KiB
C++
860 lines
22 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cmath>
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#include <cstdio>
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#include <cstdlib>
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#include <iostream>
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#include <iomanip>
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#include <list>
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#include <sstream>
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#include <string>
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/trace.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/full_cpu/smt.hh"
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#include "cpu/simple_cpu/simple_cpu.hh"
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#include "cpu/static_inst.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "sim/annotation.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#ifdef FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "dev/alpha_access.h"
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#include "dev/pciareg.h"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "sim/system.hh"
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "eio/eio.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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void
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SimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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SimpleCPU::TickEvent::description()
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{
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return "SimpleCPU tick event";
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}
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SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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: Event(&mainEventQueue),
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cpu(_cpu)
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{
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}
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void SimpleCPU::CacheCompletionEvent::process()
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{
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cpu->processCacheCompletion();
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}
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const char *
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SimpleCPU::CacheCompletionEvent::description()
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{
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return "SimpleCPU cache completion event";
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}
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#ifdef FULL_SYSTEM
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SimpleCPU::SimpleCPU(const string &_name,
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System *_system,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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AlphaITB *itb, AlphaDTB *dtb,
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FunctionalMemory *mem,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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bool _def_reg, Tick freq)
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: BaseCPU(_name, /* number_of_threads */ 1,
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max_insts_any_thread, max_insts_all_threads,
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max_loads_any_thread, max_loads_all_threads,
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_system, freq),
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#else
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SimpleCPU::SimpleCPU(const string &_name, Process *_process,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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bool _def_reg)
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: BaseCPU(_name, /* number_of_threads */ 1,
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max_insts_any_thread, max_insts_all_threads,
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max_loads_any_thread, max_loads_all_threads),
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#endif
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tickEvent(this), xc(NULL), defer_registration(_def_reg),
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cacheCompletionEvent(this)
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{
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_status = Idle;
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#ifdef FULL_SYSTEM
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xc = new ExecContext(this, 0, system, itb, dtb, mem);
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// initialize CPU, including PC
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TheISA::initCPU(&xc->regs);
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#else
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xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
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#endif // !FULL_SYSTEM
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icacheInterface = icache_interface;
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dcacheInterface = dcache_interface;
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memReq = new MemReq();
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memReq->xc = xc;
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memReq->asid = 0;
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memReq->data = new uint8_t[64];
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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execContexts.push_back(xc);
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}
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SimpleCPU::~SimpleCPU()
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{
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}
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void SimpleCPU::init()
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{
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if (!defer_registration) {
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this->registerExecContexts();
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}
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}
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void
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SimpleCPU::switchOut()
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{
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_status = SwitchedOut;
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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void
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SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ExecContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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oldCPU->switchOut();
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}
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void
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SimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Idle);
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notIdleFraction++;
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scheduleTickEvent(delay);
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_status = Running;
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}
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void
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SimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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}
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void
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SimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::regStats()
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{
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using namespace Statistics;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
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simInsts += numInsts;
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}
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void
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SimpleCPU::resetStats()
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{
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startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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void
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SimpleCPU::serialize(ostream &os)
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{
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SERIALIZE_ENUM(_status);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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xc->serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
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cacheCompletionEvent.serialize(os);
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}
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void
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SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_ENUM(_status);
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UNSERIALIZE_SCALAR(inst);
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xc->unserialize(cp, csprintf("%s.xc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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cacheCompletionEvent
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.unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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SimpleCPU::copySrcTranslate(Addr src)
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{
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memReq->reset(src, (dcacheInterface) ?
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dcacheInterface->getBlockSize()
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: 64);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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if (fault == No_Fault) {
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xc->copySrcAddr = src;
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xc->copySrcPhysAddr = memReq->paddr;
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} else {
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xc->copySrcAddr = 0;
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xc->copySrcPhysAddr = 0;
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}
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return fault;
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}
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Fault
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SimpleCPU::copy(Addr dest)
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{
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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uint8_t data[blk_size];
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assert(xc->copySrcPhysAddr);
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memReq->reset(dest, blk_size);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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if (fault == No_Fault) {
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Addr dest_addr = memReq->paddr;
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// Need to read straight from memory since we have more than 8 bytes.
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memReq->paddr = xc->copySrcPhysAddr;
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xc->mem->read(memReq, data);
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memReq->paddr = dest_addr;
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xc->mem->write(memReq, data);
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}
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return fault;
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}
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// precise architected memory state accessor macros
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template <class T>
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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// if we have a cache, do cache access too
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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unscheduleTickEvent();
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_status = DcacheMissStall;
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}
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}
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->write(memReq, data);
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Write;
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memcpy(memReq->data,(uint8_t *)&data,memReq->size);
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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unscheduleTickEvent();
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_status = DcacheMissStall;
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}
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}
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if (res && (fault == No_Fault))
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*res = memReq->result;
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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|
return write(*(uint32_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write((uint32_t)data, addr, flags, res);
|
|
}
|
|
|
|
|
|
#ifdef FULL_SYSTEM
|
|
Addr
|
|
SimpleCPU::dbg_vtophys(Addr addr)
|
|
{
|
|
return vtophys(xc, addr);
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
Tick save_cycle = 0;
|
|
|
|
|
|
void
|
|
SimpleCPU::processCacheCompletion()
|
|
{
|
|
switch (status()) {
|
|
case IcacheMissStall:
|
|
icacheStallCycles += curTick - lastIcacheStall;
|
|
_status = IcacheMissComplete;
|
|
scheduleTickEvent(1);
|
|
break;
|
|
case DcacheMissStall:
|
|
dcacheStallCycles += curTick - lastDcacheStall;
|
|
_status = Running;
|
|
scheduleTickEvent(1);
|
|
break;
|
|
case SwitchedOut:
|
|
// If this CPU has been switched out due to sampling/warm-up,
|
|
// ignore any further status changes (e.g., due to cache
|
|
// misses outstanding at the time of the switch).
|
|
return;
|
|
default:
|
|
panic("SimpleCPU::processCacheCompletion: bad state");
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef FULL_SYSTEM
|
|
void
|
|
SimpleCPU::post_interrupt(int int_num, int index)
|
|
{
|
|
BaseCPU::post_interrupt(int_num, index);
|
|
|
|
if (xc->status() == ExecContext::Suspended) {
|
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
|
xc->activate();
|
|
Annotate::Resume(xc);
|
|
}
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
/* start simulation, program loaded, processor precise state initialized */
|
|
void
|
|
SimpleCPU::tick()
|
|
{
|
|
traceData = NULL;
|
|
|
|
Fault fault = No_Fault;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
if (AlphaISA::check_interrupts &&
|
|
xc->cpu->check_interrupts() &&
|
|
!PC_PAL(xc->regs.pc) &&
|
|
status() != IcacheMissComplete) {
|
|
int ipl = 0;
|
|
int summary = 0;
|
|
AlphaISA::check_interrupts = 0;
|
|
IntReg *ipr = xc->regs.ipr;
|
|
|
|
if (xc->regs.ipr[TheISA::IPR_SIRR]) {
|
|
for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
|
|
i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
|
|
if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
}
|
|
|
|
uint64_t interrupts = xc->cpu->intr_status();
|
|
for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
|
|
i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
|
|
if (interrupts & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = i;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
|
|
if (ipr[TheISA::IPR_ASTRR])
|
|
panic("asynchronous traps not implemented\n");
|
|
|
|
if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
|
|
ipr[TheISA::IPR_ISR] = summary;
|
|
ipr[TheISA::IPR_INTID] = ipl;
|
|
xc->ev5_trap(Interrupt_Fault);
|
|
|
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
|
ipr[TheISA::IPR_IPLR], ipl, summary);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// maintain $r0 semantics
|
|
xc->regs.intRegFile[ZeroReg] = 0;
|
|
#ifdef TARGET_ALPHA
|
|
xc->regs.floatRegFile.d[ZeroReg] = 0.0;
|
|
#endif // TARGET_ALPHA
|
|
|
|
if (status() == IcacheMissComplete) {
|
|
// We've already fetched an instruction and were stalled on an
|
|
// I-cache miss. No need to fetch it again.
|
|
|
|
// Set status to running; tick event will get rescheduled if
|
|
// necessary at end of tick() function.
|
|
_status = Running;
|
|
}
|
|
else {
|
|
// Try to fetch an instruction
|
|
|
|
// set up memory request for instruction fetch
|
|
#ifdef FULL_SYSTEM
|
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
|
#else
|
|
#define IFETCH_FLAGS(pc) 0
|
|
#endif
|
|
|
|
memReq->cmd = Read;
|
|
memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
|
|
IFETCH_FLAGS(xc->regs.pc));
|
|
|
|
fault = xc->translateInstReq(memReq);
|
|
|
|
if (fault == No_Fault)
|
|
fault = xc->mem->read(memReq, inst);
|
|
|
|
if (icacheInterface && fault == No_Fault) {
|
|
memReq->completionEvent = NULL;
|
|
|
|
memReq->time = curTick;
|
|
MemAccessResult result = icacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && icacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastIcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = IcacheMissStall;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
// If we've got a valid instruction (i.e., no fault on instruction
|
|
// fetch), then execute it.
|
|
if (fault == No_Fault) {
|
|
|
|
// keep an instruction count
|
|
numInst++;
|
|
|
|
// check for instruction-count-based events
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
// decode the instruction
|
|
StaticInstPtr<TheISA> si(inst);
|
|
|
|
traceData = Trace::getInstRecord(curTick, xc, this, si,
|
|
xc->regs.pc);
|
|
|
|
#ifdef FULL_SYSTEM
|
|
xc->regs.opcode = (inst >> 26) & 0x3f;
|
|
xc->regs.ra = (inst >> 21) & 0x1f;
|
|
#endif // FULL_SYSTEM
|
|
|
|
xc->func_exe_inst++;
|
|
|
|
fault = si->execute(this, xc, traceData);
|
|
|
|
#ifdef FULL_SYSTEM
|
|
SWContext *ctx = xc->swCtx;
|
|
if (ctx)
|
|
ctx->process(xc, si.get());
|
|
#endif
|
|
|
|
if (si->isMemRef()) {
|
|
numMemRefs++;
|
|
}
|
|
|
|
if (si->isLoad()) {
|
|
++numLoad;
|
|
comLoadEventQueue[0]->serviceEvents(numLoad);
|
|
}
|
|
|
|
if (traceData)
|
|
traceData->finalize();
|
|
|
|
} // if (fault == No_Fault)
|
|
|
|
if (fault != No_Fault) {
|
|
#ifdef FULL_SYSTEM
|
|
xc->ev5_trap(fault);
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
else {
|
|
// go to the next instruction
|
|
xc->regs.pc = xc->regs.npc;
|
|
xc->regs.npc += sizeof(MachInst);
|
|
}
|
|
|
|
#ifdef FULL_SYSTEM
|
|
Addr oldpc;
|
|
do {
|
|
oldpc = xc->regs.pc;
|
|
system->pcEventQueue.service(xc);
|
|
} while (oldpc != xc->regs.pc);
|
|
#endif
|
|
|
|
assert(status() == Running ||
|
|
status() == Idle ||
|
|
status() == DcacheMissStall);
|
|
|
|
if (status() == Running && !tickEvent.scheduled())
|
|
tickEvent.schedule(curTick + 1);
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// SimpleCPU Simulation Object
|
|
//
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
#ifdef FULL_SYSTEM
|
|
SimObjectParam<AlphaITB *> itb;
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
SimObjectParam<FunctionalMemory *> mem;
|
|
SimObjectParam<System *> system;
|
|
Param<int> mult;
|
|
#else
|
|
SimObjectParam<Process *> workload;
|
|
#endif // FULL_SYSTEM
|
|
|
|
SimObjectParam<BaseMem *> icache;
|
|
SimObjectParam<BaseMem *> dcache;
|
|
|
|
Param<bool> defer_registration;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
|
"terminate when any thread reaches this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
|
"terminate when all threads have reached this inst count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
|
"terminate when any thread reaches this load count",
|
|
0),
|
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
|
"terminate when all threads have reached this load count",
|
|
0),
|
|
|
|
#ifdef FULL_SYSTEM
|
|
INIT_PARAM(itb, "Instruction TLB"),
|
|
INIT_PARAM(dtb, "Data TLB"),
|
|
INIT_PARAM(mem, "memory"),
|
|
INIT_PARAM(system, "system object"),
|
|
INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
|
|
#else
|
|
INIT_PARAM(workload, "processes to run"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
|
|
INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
|
|
INIT_PARAM_DFLT(defer_registration, "defer registration with system "
|
|
"(for sampling)", false)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
|
|
CREATE_SIM_OBJECT(SimpleCPU)
|
|
{
|
|
SimpleCPU *cpu;
|
|
#ifdef FULL_SYSTEM
|
|
if (mult != 1)
|
|
panic("processor clock multiplier must be 1\n");
|
|
|
|
cpu = new SimpleCPU(getInstanceName(), system,
|
|
max_insts_any_thread, max_insts_all_threads,
|
|
max_loads_any_thread, max_loads_all_threads,
|
|
itb, dtb, mem,
|
|
(icache) ? icache->getInterface() : NULL,
|
|
(dcache) ? dcache->getInterface() : NULL,
|
|
defer_registration,
|
|
ticksPerSecond * mult);
|
|
#else
|
|
|
|
cpu = new SimpleCPU(getInstanceName(), workload,
|
|
max_insts_any_thread, max_insts_all_threads,
|
|
max_loads_any_thread, max_loads_all_threads,
|
|
(icache) ? icache->getInterface() : NULL,
|
|
(dcache) ? dcache->getInterface() : NULL,
|
|
defer_registration);
|
|
|
|
#endif // FULL_SYSTEM
|
|
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
|
|
|