src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
190 lines
6.1 KiB
C++
190 lines
6.1 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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*/
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#include "arch/mips/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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#if !FULL_SYSTEM
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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#endif
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namespace MipsISA
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{
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FaultName MachineCheckFault::_name = "Machine Check";
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "Alignment";
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_count;
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FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable";
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FaultVect CoprocessorUnusableFault::_vect = 0xF001;
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FaultStat CoprocessorUnusableFault::_count;
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FaultName ReservedInstructionFault::_name = "Reserved Instruction";
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FaultVect ReservedInstructionFault::_vect = 0x0F01;
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FaultStat ReservedInstructionFault::_count;
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FaultName ThreadFault::_name = "thread";
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FaultVect ThreadFault::_vect = 0x00F1;
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FaultStat ThreadFault::_count;
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FaultName ArithmeticFault::_name = "arith";
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultStat ArithmeticFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_count;
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#if !FULL_SYSTEM
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//FaultName PageTableFault::_name = "page_table_fault";
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//FaultVect PageTableFault::_vect = 0x0000;
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//FaultStat PageTableFault::_count;
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#endif
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0101;
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FaultStat InterruptFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_count;
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FaultName FloatEnableFault::_name = "fen";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_count;
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FaultName IntegerOverflowFault::_name = "intover";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_count;
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FaultName DspStateDisabledFault::_name = "intover";
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FaultVect DspStateDisabledFault::_vect = 0x001a;
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FaultStat DspStateDisabledFault::_count;
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/*void PageTableFault::invoke(ThreadContext *tc)
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{
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Process *p = tc->getProcessPtr();
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Addr page_addr = p->pTable->pageAlign(vaddr);
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warn("%i: [tid:%i]: %s encountered @ addr %x. Allocating new page for address range %x - %x.\n",
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curTick, tc->getThreadNum(), name(), vaddr, page_addr, page_addr+VMPageSize);
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p->pTable->allocate(page_addr, VMPageSize);
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return;
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}
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*/
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/* address is higher than the stack region or in the current stack region
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if (vaddr > p->stack_base || vaddr > p->stack_min)
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FaultBase::invoke(tc);
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// We've accessed the next page
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if (vaddr > p->stack_min - PageBytes) {
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p->stack_min -= PageBytes;
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if (p->stack_base - p->stack_min > 8*1024*1024) {
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warn("Already allocated Over max stack size for one thread\n");
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}
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warn("%i: Allocating page for range %x - %x",
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curTick, p->stack_min, p->stack_min-PageBytes);
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p->pTable->allocate(p->stack_min, PageBytes);
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warn("Increasing stack size by one page.");
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} else {
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FaultBase::invoke(tc);
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}*/
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void ResetFault::invoke(ThreadContext *tc)
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{
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warn("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
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//tc->getCpuPtr()->reset();
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}
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void CoprocessorUnusableFault::invoke(ThreadContext *tc)
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{
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panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
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}
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void ReservedInstructionFault::invoke(ThreadContext *tc)
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{
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panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
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}
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void ThreadFault::invoke(ThreadContext *tc)
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{
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panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
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}
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void DspStateDisabledFault::invoke(ThreadContext *tc)
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{
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panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
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}
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} // namespace MipsISA
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