132 lines
4 KiB
C++
132 lines
4 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Korey Sewell
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*/
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#ifndef __ARCH_MIPS_UTILITY_HH__
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#define __ARCH_MIPS_UTILITY_HH__
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/types.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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class ThreadContext;
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namespace MipsISA {
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inline PCState
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buildRetPC(const PCState &curPC, const PCState &callPC)
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{
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PCState ret = callPC;
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ret.advance();
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ret.pc(curPC.npc());
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return ret;
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}
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uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
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////////////////////////////////////////////////////////////////////////
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//
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// Floating Point Utility Functions
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//
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uint64_t fpConvert(ConvertType cvt_type, double fp_val);
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double roundFP(double val, int digits);
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double truncFP(double val);
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bool getCondCode(uint32_t fcsr, int cc);
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uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
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uint32_t genInvalidVector(uint32_t fcsr);
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bool isNan(void *val_ptr, int size);
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bool isQnan(void *val_ptr, int size);
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bool isSnan(void *val_ptr, int size);
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static inline bool
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inUserMode(ThreadContext *tc)
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{
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MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
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MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
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if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
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(Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible
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(Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
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// Unable to use Status_CU0, etc directly, using bitfields & masks
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return true;
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} else {
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return false;
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}
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}
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template <class CPU>
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void zeroRegisters(CPU *cpu);
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(PageBytes - 1); }
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inline Addr
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RoundPage(Addr addr)
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{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
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////////////////////////////////////////////////////////////////////////
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//
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// CPU Utility
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//
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void startupCPU(ThreadContext *tc, int cpuId);
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void initCPU(ThreadContext *tc, int cpuId);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void skipFunction(ThreadContext *tc);
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inline void
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advancePC(PCState &pc, const StaticInstPtr inst)
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{
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pc.advance();
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}
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inline uint64_t
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getExecutingAsid(ThreadContext *tc)
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{
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return 0;
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}
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};
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#endif
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