5efbb4442a
This patch enables the use of page tables that are stored in system memory and respect x86 specification, in SE mode. It defines an architectural page table for x86 as a MultiLevelPageTable class and puts a placeholder class for other ISAs page tables, giving the possibility for future implementation.
218 lines
6.8 KiB
C++
218 lines
6.8 KiB
C++
/*
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* Copyright (c) 2014 Advanced Micro Devices, Inc.
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_PAGETABLE_HH__
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#define __ARCH_X86_PAGETABLE_HH__
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#include <iostream>
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#include <string>
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#include <vector>
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#include "base/bitunion.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "base/trie.hh"
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#include "cpu/thread_context.hh"
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#include "arch/x86/system.hh"
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#include "debug/MMU.hh"
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class Checkpoint;
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namespace X86ISA
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{
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struct TlbEntry;
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}
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typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
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namespace X86ISA
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{
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BitUnion64(VAddr)
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Bitfield<20, 12> longl1;
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Bitfield<29, 21> longl2;
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Bitfield<38, 30> longl3;
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Bitfield<47, 39> longl4;
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Bitfield<20, 12> pael1;
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Bitfield<29, 21> pael2;
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Bitfield<31, 30> pael3;
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Bitfield<21, 12> norml1;
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Bitfield<31, 22> norml2;
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EndBitUnion(VAddr)
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// Unfortunately, the placement of the base field in a page table entry is
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// very erratic and would make a mess here. It might be moved here at some
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// point in the future.
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BitUnion64(PageTableEntry)
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Bitfield<63> nx;
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Bitfield<51, 12> base;
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Bitfield<11, 9> avl;
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Bitfield<8> g;
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Bitfield<7> ps;
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Bitfield<6> d;
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Bitfield<5> a;
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Bitfield<4> pcd;
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Bitfield<3> pwt;
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Bitfield<2> u;
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Bitfield<1> w;
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Bitfield<0> p;
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EndBitUnion(PageTableEntry)
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struct TlbEntry
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{
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// The base of the physical page.
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Addr paddr;
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// The beginning of the virtual page this entry maps.
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Addr vaddr;
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// The size of the page this represents, in address bits.
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unsigned logBytes;
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// Read permission is always available, assuming it isn't blocked by
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// other mechanisms.
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bool writable;
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// Whether this page is accesible without being in supervisor mode.
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bool user;
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// Whether to use write through or write back. M5 ignores this and
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// lets the caches handle the writeback policy.
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//bool pwt;
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// Whether the page is cacheable or not.
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bool uncacheable;
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// Whether or not to kick this page out on a write to CR3.
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bool global;
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// A bit used to form an index into the PAT table.
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bool patBit;
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// Whether or not memory on this page can be executed.
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bool noExec;
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// A sequence number to keep track of LRU.
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uint64_t lruSeq;
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TlbEntryTrie::Handle trieHandle;
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TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
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TlbEntry() {}
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void
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updateVaddr(Addr new_vaddr)
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{
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vaddr = new_vaddr;
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}
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Addr pageStart()
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{
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return paddr;
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}
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// Return the page size in bytes
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int size()
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{
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return (1 << logBytes);
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/** The size of each level of the page table expressed in base 2
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* logarithmic values
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*/
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const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
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enum PTEField{
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PTE_NotPresent = 0,
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PTE_Present,
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PTE_ReadOnly = 0,
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PTE_ReadWrite,
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PTE_Supervisor = 0,
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PTE_UserSupervisor,
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};
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/** Page table operations specific to x86 ISA.
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* Indended to be used as parameter of MultiLevelPageTable.
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*/
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class PageTableOps
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{
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public:
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void setPTEFields(PageTableEntry& PTE,
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uint64_t present = PTE_Present,
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uint64_t read_write = PTE_ReadWrite,
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uint64_t user_supervisor = PTE_UserSupervisor)
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{
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PTE.p = present;
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PTE.w = read_write;
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PTE.u = user_supervisor;// both user and supervisor access allowed
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}
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/** returns the physical memory address of the page table */
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Addr getBasePtr(ThreadContext* tc)
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{
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CR3 cr3 = pageTablePhysAddr;
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DPRINTF(MMU, "CR3: %d\n", cr3);
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return cr3.longPdtb;
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}
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/** returns the page number out of a page table entry */
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Addr getPnum(PageTableEntry PTE)
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{
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return PTE.base;
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}
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/** sets the page number in a page table entry */
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void setPnum(PageTableEntry& PTE, Addr paddr)
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{
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PTE.base = paddr;
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}
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/** returns the offsets to index in every level of a page
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* table, contained in a virtual address
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*/
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std::vector<uint64_t> getOffsets(Addr vaddr)
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{
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X86ISA::VAddr addr(vaddr);
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return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
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}
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};
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}
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#endif
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