25ec278a0b
The changes made by the changeset 9376 were not quite correct. The patch made changes to the code which resulted in decoder not getting initialized correctly when the state was restored from a checkpoint. This patch adds a startup function to each ISA object. For x86, this function sets the required state in the decoder. For other ISAs, the function is empty right now.
403 lines
12 KiB
C++
403 lines
12 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/decoder.hh"
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#include "arch/x86/isa.hh"
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#include "arch/x86/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "params/X86ISA.hh"
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#include "sim/serialize.hh"
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namespace X86ISA
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{
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void
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ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
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ThreadContext *tc)
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{
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HandyM5Reg m5reg = 0;
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if (efer.lma) {
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m5reg.mode = LongMode;
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if (csAttr.longMode)
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m5reg.submode = SixtyFourBitMode;
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else
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m5reg.submode = CompatabilityMode;
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} else {
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m5reg.mode = LegacyMode;
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if (cr0.pe) {
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if (rflags.vm)
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m5reg.submode = Virtual8086Mode;
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else
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m5reg.submode = ProtectedMode;
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} else {
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m5reg.submode = RealMode;
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}
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}
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m5reg.cpl = csAttr.dpl;
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m5reg.paging = cr0.pg;
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m5reg.prot = cr0.pe;
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// Compute the default and alternate operand size.
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if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
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m5reg.defOp = 2;
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m5reg.altOp = 1;
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} else {
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m5reg.defOp = 1;
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m5reg.altOp = 2;
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}
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// Compute the default and alternate address size.
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if (m5reg.submode == SixtyFourBitMode) {
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m5reg.defAddr = 3;
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m5reg.altAddr = 2;
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} else if (csAttr.defaultSize) {
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m5reg.defAddr = 2;
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m5reg.altAddr = 1;
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} else {
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m5reg.defAddr = 1;
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m5reg.altAddr = 2;
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}
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// Compute the stack size
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if (m5reg.submode == SixtyFourBitMode) {
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m5reg.stack = 3;
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} else if (ssAttr.defaultSize) {
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m5reg.stack = 2;
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} else {
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m5reg.stack = 1;
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}
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regVal[MISCREG_M5_REG] = m5reg;
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if (tc)
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tc->getDecoderPtr()->setM5Reg(m5reg);
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}
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void
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ISA::clear()
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{
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// Blank everything. 0 might not be an appropriate value for some things,
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// but it is for most.
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memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
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regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
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regVal[MISCREG_DR7] = 1 << 10;
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}
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ISA::ISA(Params *p)
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: SimObject(p)
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{
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clear();
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}
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const X86ISAParams *
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ISA::params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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MiscReg
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ISA::readMiscRegNoEffect(int miscReg)
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{
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// Make sure we're not dealing with an illegal control register.
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// Instructions should filter out these indexes, and nothing else should
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// attempt to read them directly.
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assert( miscReg != MISCREG_CR1 &&
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!(miscReg > MISCREG_CR4 &&
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miscReg < MISCREG_CR8) &&
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!(miscReg > MISCREG_CR8 &&
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miscReg <= MISCREG_CR15));
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return regVal[miscReg];
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}
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MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext * tc)
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{
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if (miscReg == MISCREG_TSC) {
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return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
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}
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if (miscReg == MISCREG_FSW) {
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MiscReg fsw = regVal[MISCREG_FSW];
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MiscReg top = regVal[MISCREG_X87_TOP];
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return (fsw & (~(7ULL << 11))) + (top << 11);
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}
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return readMiscRegNoEffect(miscReg);
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}
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void
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ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
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{
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// Make sure we're not dealing with an illegal control register.
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// Instructions should filter out these indexes, and nothing else should
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// attempt to write to them directly.
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assert( miscReg != MISCREG_CR1 &&
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!(miscReg > MISCREG_CR4 &&
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miscReg < MISCREG_CR8) &&
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!(miscReg > MISCREG_CR8 &&
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miscReg <= MISCREG_CR15));
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regVal[miscReg] = val;
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}
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void
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ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
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{
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MiscReg newVal = val;
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switch(miscReg)
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{
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case MISCREG_CR0:
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{
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CR0 toggled = regVal[miscReg] ^ val;
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CR0 newCR0 = val;
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Efer efer = regVal[MISCREG_EFER];
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if (toggled.pg && efer.lme) {
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if (newCR0.pg) {
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//Turning on long mode
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efer.lma = 1;
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regVal[MISCREG_EFER] = efer;
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} else {
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//Turning off long mode
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efer.lma = 0;
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regVal[MISCREG_EFER] = efer;
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}
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}
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if (toggled.pg) {
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tc->getITBPtr()->flushAll();
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tc->getDTBPtr()->flushAll();
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}
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//This must always be 1.
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newCR0.et = 1;
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newVal = newCR0;
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updateHandyM5Reg(regVal[MISCREG_EFER],
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newCR0,
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regVal[MISCREG_CS_ATTR],
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS],
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tc);
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}
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break;
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case MISCREG_CR2:
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break;
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case MISCREG_CR3:
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tc->getITBPtr()->flushNonGlobal();
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tc->getDTBPtr()->flushNonGlobal();
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break;
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case MISCREG_CR4:
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{
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CR4 toggled = regVal[miscReg] ^ val;
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if (toggled.pae || toggled.pse || toggled.pge) {
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tc->getITBPtr()->flushAll();
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tc->getDTBPtr()->flushAll();
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}
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}
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break;
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case MISCREG_CR8:
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break;
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case MISCREG_CS_ATTR:
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{
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SegAttr toggled = regVal[miscReg] ^ val;
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SegAttr newCSAttr = val;
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if (toggled.longMode) {
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if (newCSAttr.longMode) {
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regVal[MISCREG_ES_EFF_BASE] = 0;
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regVal[MISCREG_CS_EFF_BASE] = 0;
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regVal[MISCREG_SS_EFF_BASE] = 0;
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regVal[MISCREG_DS_EFF_BASE] = 0;
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} else {
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regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
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regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
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regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
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regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
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}
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}
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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newCSAttr,
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS],
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tc);
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}
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break;
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case MISCREG_SS_ATTR:
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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regVal[MISCREG_CS_ATTR],
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val,
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regVal[MISCREG_RFLAGS],
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tc);
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break;
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// These segments always actually use their bases, or in other words
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// their effective bases must stay equal to their actual bases.
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case MISCREG_FS_BASE:
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case MISCREG_GS_BASE:
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case MISCREG_HS_BASE:
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case MISCREG_TSL_BASE:
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case MISCREG_TSG_BASE:
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case MISCREG_TR_BASE:
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case MISCREG_IDTR_BASE:
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regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
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break;
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// These segments ignore their bases in 64 bit mode.
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// their effective bases must stay equal to their actual bases.
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case MISCREG_ES_BASE:
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case MISCREG_CS_BASE:
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case MISCREG_SS_BASE:
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case MISCREG_DS_BASE:
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{
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Efer efer = regVal[MISCREG_EFER];
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SegAttr csAttr = regVal[MISCREG_CS_ATTR];
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if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
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regVal[MISCREG_SEG_EFF_BASE(miscReg -
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MISCREG_SEG_BASE_BASE)] = val;
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}
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break;
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case MISCREG_TSC:
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regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
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return;
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case MISCREG_DR0:
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case MISCREG_DR1:
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case MISCREG_DR2:
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case MISCREG_DR3:
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/* These should eventually set up breakpoints. */
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break;
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case MISCREG_DR4:
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miscReg = MISCREG_DR6;
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/* Fall through to have the same effects as DR6. */
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case MISCREG_DR6:
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{
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DR6 dr6 = regVal[MISCREG_DR6];
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DR6 newDR6 = val;
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dr6.b0 = newDR6.b0;
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dr6.b1 = newDR6.b1;
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dr6.b2 = newDR6.b2;
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dr6.b3 = newDR6.b3;
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dr6.bd = newDR6.bd;
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dr6.bs = newDR6.bs;
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dr6.bt = newDR6.bt;
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newVal = dr6;
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}
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break;
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case MISCREG_DR5:
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miscReg = MISCREG_DR7;
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/* Fall through to have the same effects as DR7. */
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case MISCREG_DR7:
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{
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DR7 dr7 = regVal[MISCREG_DR7];
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DR7 newDR7 = val;
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dr7.l0 = newDR7.l0;
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dr7.g0 = newDR7.g0;
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if (dr7.l0 || dr7.g0) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 0. */
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}
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dr7.l1 = newDR7.l1;
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dr7.g1 = newDR7.g1;
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if (dr7.l1 || dr7.g1) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 1. */
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}
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dr7.l2 = newDR7.l2;
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dr7.g2 = newDR7.g2;
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if (dr7.l2 || dr7.g2) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 2. */
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}
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dr7.l3 = newDR7.l3;
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dr7.g3 = newDR7.g3;
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if (dr7.l3 || dr7.g3) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 3. */
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}
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dr7.gd = newDR7.gd;
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dr7.rw0 = newDR7.rw0;
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dr7.len0 = newDR7.len0;
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dr7.rw1 = newDR7.rw1;
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dr7.len1 = newDR7.len1;
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dr7.rw2 = newDR7.rw2;
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dr7.len2 = newDR7.len2;
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dr7.rw3 = newDR7.rw3;
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dr7.len3 = newDR7.len3;
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}
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break;
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case MISCREG_M5_REG:
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// Writing anything to the m5reg with side effects makes it update
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// based on the current values of the relevant registers. The actual
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// value written is discarded.
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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regVal[MISCREG_CS_ATTR],
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS],
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tc);
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return;
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default:
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break;
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}
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setMiscRegNoEffect(miscReg, newVal);
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}
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void
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ISA::serialize(std::ostream & os)
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{
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SERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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void
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ISA::unserialize(Checkpoint * cp, const std::string & section)
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{
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UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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regVal[MISCREG_CS_ATTR],
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS],
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NULL);
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}
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void
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ISA::startup(ThreadContext *tc)
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{
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tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
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}
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}
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X86ISA::ISA *
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X86ISAParams::create()
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{
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return new X86ISA::ISA(this);
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}
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