ced021a78f
dev/ide_disk.cc:
Fix to PIO writes and also add command needed for shutdown
dev/pcidev.cc:
Change the panic on write to read-only registers to a debug print. The
kernel tries to write back over all of the PCI registers to restore
the saved SRM state, so we need to let it do this without panicing.
sim/system.cc:
Add back increment of number of running systems to allow trap of halt
work correctly.
--HG--
extra : convert_revision : 84aba4effbec14545f3610c19a8e321d7e7f7cf2
388 lines
14 KiB
C++
388 lines
14 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* A single PCI device configuration space entry.
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*/
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#include <list>
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#include <sstream>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/misc.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/pciareg.h"
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#include "dev/pcidev.hh"
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#include "dev/pciconfigall.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/param.hh"
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#include "sim/universe.hh"
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#include "dev/tsunamireg.h"
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using namespace std;
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PciDev::PciDev(const string &name, MemoryController *mmu, PciConfigAll *cf,
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PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
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: DmaDevice(name), mmu(mmu), configSpace(cf), configData(cd), busNum(bus),
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deviceNum(dev), functionNum(func)
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{
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// copy the config data from the PciConfigData object
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if (cd) {
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memcpy(config.data, cd->config.data, sizeof(config.data));
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memcpy(BARSize, cd->BARSize, sizeof(BARSize));
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memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
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} else
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panic("NULL pointer to configuration data");
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// Setup pointer in config space to point to this entry
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if (cf->devices[dev][func] != NULL)
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panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
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else
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cf->devices[dev][func] = this;
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}
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void
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PciDev::ReadConfig(int offset, int size, uint8_t *data)
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{
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switch(size) {
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case sizeof(uint32_t):
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memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
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DPRINTF(PCIDEV,
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"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
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deviceNum, functionNum, offset, size,
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*(uint32_t*)(config.data + offset));
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break;
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case sizeof(uint16_t):
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memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
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DPRINTF(PCIDEV,
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"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
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deviceNum, functionNum, offset, size,
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*(uint16_t*)(config.data + offset));
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break;
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case sizeof(uint8_t):
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memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
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DPRINTF(PCIDEV,
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"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
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deviceNum, functionNum, offset, size,
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(uint16_t)(*(uint8_t*)(config.data + offset)));
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break;
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default:
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panic("Invalid Read Size");
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}
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}
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void
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PciDev::WriteConfig(int offset, int size, uint32_t data)
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{
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uint32_t barnum;
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union {
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uint8_t byte_value;
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uint16_t half_value;
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uint32_t word_value;
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};
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word_value = data;
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DPRINTF(PCIDEV,
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"write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
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deviceNum, functionNum, offset, size, word_value);
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barnum = (offset - PCI0_BASE_ADDR0) >> 2;
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switch (size) {
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case sizeof(uint8_t): // 1-byte access
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switch (offset) {
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case PCI0_INTERRUPT_LINE:
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case PCI_CACHE_LINE_SIZE:
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case PCI_LATENCY_TIMER:
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*(uint8_t *)&config.data[offset] = byte_value;
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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case sizeof(uint16_t): // 2-byte access
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switch (offset) {
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case PCI_COMMAND:
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case PCI_STATUS:
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case PCI_CACHE_LINE_SIZE:
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*(uint16_t *)&config.data[offset] = half_value;
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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case sizeof(uint16_t)+1: // 3-byte access
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panic("invalid access size");
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case sizeof(uint32_t): // 4-byte access
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR1:
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case PCI0_BASE_ADDR2:
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case PCI0_BASE_ADDR3:
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case PCI0_BASE_ADDR4:
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case PCI0_BASE_ADDR5:
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// Writing 0xffffffff to a BAR tells the card to set the
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// value of the bar
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// to size of memory it needs
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if (word_value == 0xffffffff) {
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// This is I/O Space, bottom two bits are read only
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if (config.data[offset] & 0x1) {
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*(uint32_t *)&config.data[offset] =
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~(BARSize[barnum] - 1) |
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(config.data[offset] & 0x3);
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} else {
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// This is memory space, bottom four bits are read only
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*(uint32_t *)&config.data[offset] =
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~(BARSize[barnum] - 1) |
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(config.data[offset] & 0xF);
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}
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} else {
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// This is I/O Space, bottom two bits are read only
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if(config.data[offset] & 0x1) {
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*(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
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(config.data[offset] & 0x3);
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if (word_value & ~0x1) {
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Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
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Addr base_size = BARSize[barnum]-1;
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// It's never been set
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if (BARAddrs[barnum] == 0)
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mmu->add_child((FunctionalMemory *)this,
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Range<Addr>(base_addr,
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base_addr + base_size));
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else
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mmu->update_child((FunctionalMemory *)this,
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Range<Addr>(BARAddrs[barnum],
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BARAddrs[barnum] +
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base_size),
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Range<Addr>(base_addr,
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base_addr +
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base_size));
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BARAddrs[barnum] = base_addr;
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}
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} else {
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// This is memory space, bottom four bits are read only
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*(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
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(config.data[offset] & 0xF);
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if (word_value & ~0x3) {
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Addr base_addr = (word_value & ~0x3) +
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TSUNAMI_PCI0_MEMORY;
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Addr base_size = BARSize[barnum]-1;
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// It's never been set
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if (BARAddrs[barnum] == 0)
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mmu->add_child((FunctionalMemory *)this,
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Range<Addr>(base_addr,
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base_addr + base_size));
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else
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mmu->update_child((FunctionalMemory *)this,
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Range<Addr>(BARAddrs[barnum],
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BARAddrs[barnum] +
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base_size),
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Range<Addr>(base_addr,
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base_addr +
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base_size));
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BARAddrs[barnum] = base_addr;
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}
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}
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}
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break;
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case PCI0_ROM_BASE_ADDR:
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if (word_value == 0xfffffffe)
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*(uint32_t *)&config.data[offset] = 0xffffffff;
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else
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*(uint32_t *)&config.data[offset] = word_value;
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break;
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case PCI_COMMAND:
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// This could also clear some of the error bits in the Status
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// register. However they should never get set, so lets ignore
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// it for now
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*(uint16_t *)&config.data[offset] = half_value;
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break;
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default:
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DPRINTF(PCIDEV, "Writing to a read only register");
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}
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break;
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}
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}
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void
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PciDev::serialize(ostream &os)
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{
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SERIALIZE_ARRAY(config.data, 64);
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}
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void
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PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(config.data, 64);
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
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Param<int> VendorID;
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Param<int> DeviceID;
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Param<int> Command;
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Param<int> Status;
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Param<int> Revision;
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Param<int> ProgIF;
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Param<int> SubClassCode;
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Param<int> ClassCode;
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Param<int> CacheLineSize;
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Param<int> LatencyTimer;
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Param<int> HeaderType;
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Param<int> BIST;
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Param<uint32_t> BAR0;
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Param<uint32_t> BAR1;
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Param<uint32_t> BAR2;
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Param<uint32_t> BAR3;
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Param<uint32_t> BAR4;
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Param<uint32_t> BAR5;
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Param<uint32_t> CardbusCIS;
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Param<int> SubsystemVendorID;
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Param<int> SubsystemID;
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Param<uint32_t> ExpansionROM;
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Param<int> InterruptLine;
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Param<int> InterruptPin;
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Param<int> MinimumGrant;
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Param<int> MaximumLatency;
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Param<uint32_t> BAR0Size;
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Param<uint32_t> BAR1Size;
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Param<uint32_t> BAR2Size;
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Param<uint32_t> BAR3Size;
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Param<uint32_t> BAR4Size;
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Param<uint32_t> BAR5Size;
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END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
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BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
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INIT_PARAM(VendorID, "Vendor ID"),
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INIT_PARAM(DeviceID, "Device ID"),
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INIT_PARAM_DFLT(Command, "Command Register", 0x00),
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INIT_PARAM_DFLT(Status, "Status Register", 0x00),
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INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
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INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
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INIT_PARAM(SubClassCode, "Sub-Class Code"),
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INIT_PARAM(ClassCode, "Class Code"),
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INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
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INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
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INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
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INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
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INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
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INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
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INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
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INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
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INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
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INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
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INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
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INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
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INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
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INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
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INIT_PARAM(InterruptLine, "Interrupt Line Register"),
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INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
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INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
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INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
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INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
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INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
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INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
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INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
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INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
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INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
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END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
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CREATE_SIM_OBJECT(PciConfigData)
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{
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PciConfigData *data = new PciConfigData(getInstanceName());
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data->config.hdr.vendor = VendorID;
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data->config.hdr.device = DeviceID;
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data->config.hdr.command = Command;
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data->config.hdr.status = Status;
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data->config.hdr.revision = Revision;
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data->config.hdr.progIF = ProgIF;
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data->config.hdr.subClassCode = SubClassCode;
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data->config.hdr.classCode = ClassCode;
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data->config.hdr.cacheLineSize = CacheLineSize;
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data->config.hdr.latencyTimer = LatencyTimer;
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data->config.hdr.headerType = HeaderType;
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data->config.hdr.bist = BIST;
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data->config.hdr.pci0.baseAddr0 = BAR0;
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data->config.hdr.pci0.baseAddr1 = BAR1;
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data->config.hdr.pci0.baseAddr2 = BAR2;
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data->config.hdr.pci0.baseAddr3 = BAR3;
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data->config.hdr.pci0.baseAddr4 = BAR4;
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data->config.hdr.pci0.baseAddr5 = BAR5;
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data->config.hdr.pci0.cardbusCIS = CardbusCIS;
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data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
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data->config.hdr.pci0.subsystemID = SubsystemVendorID;
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data->config.hdr.pci0.expansionROM = ExpansionROM;
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data->config.hdr.pci0.interruptLine = InterruptLine;
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data->config.hdr.pci0.interruptPin = InterruptPin;
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data->config.hdr.pci0.minimumGrant = MinimumGrant;
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data->config.hdr.pci0.maximumLatency = MaximumLatency;
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data->BARSize[0] = BAR0Size;
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data->BARSize[1] = BAR1Size;
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data->BARSize[2] = BAR2Size;
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data->BARSize[3] = BAR3Size;
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data->BARSize[4] = BAR4Size;
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data->BARSize[5] = BAR5Size;
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return data;
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}
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REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
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#endif // DOXYGEN_SHOULD_SKIP_THIS
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