818 lines
93 KiB
Text
818 lines
93 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.626015 # Number of seconds simulated
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sim_ticks 626014950000 # Number of ticks simulated
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final_tick 626014950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 71515 # Simulator instruction rate (inst/s)
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host_op_rate 71515 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 24557485 # Simulator tick rate (ticks/s)
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host_mem_usage 282608 # Number of bytes of host memory used
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host_seconds 25491.82 # Real time elapsed on the host
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sim_insts 1823043370 # Number of instructions simulated
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sim_ops 1823043370 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 30295808 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30471744 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 473372 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 476121 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 281041 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 48394704 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 48675745 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 281041 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 281041 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 6840271 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6840271 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 6840271 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 281041 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 48394704 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 55516016 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 476121 # Total number of read requests seen
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system.physmem.writeReqs 66908 # Total number of write requests seen
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system.physmem.cpureqs 543029 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 30471744 # Total number of bytes read from memory
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system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 30471744 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 29662 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 29647 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 29658 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 29696 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 29714 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 29813 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 29790 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 29697 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 29781 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 29762 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 29859 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 29815 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 626014887500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 476121 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 66908 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 406557 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 66998 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 164 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 3500552500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 21508187500 # Sum of mem lat for all requests
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system.physmem.totBusLat 2380155000 # Total cycles spent in databus access
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system.physmem.totBankLat 15627480000 # Total cycles spent in bank access
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system.physmem.avgQLat 7353.62 # Average queueing delay per request
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system.physmem.avgBankLat 32828.70 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 45182.33 # Average memory access latency
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system.physmem.avgRdBW 48.68 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 48.68 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.43 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.03 # Average read queue length over time
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system.physmem.avgWrQLen 11.00 # Average write queue length over time
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system.physmem.readRowHits 143853 # Number of row buffer hits during reads
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system.physmem.writeRowHits 46182 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 69.02 # Row buffer hit rate for writes
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system.physmem.avgGap 1152820.36 # Average gap between requests
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system.cpu.branchPred.lookups 388875863 # Number of BP lookups
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system.cpu.branchPred.condPredicted 256999007 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 25264722 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 310547770 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 257563099 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 82.938319 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 56744188 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 6782 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 519038391 # DTB read hits
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system.cpu.dtb.read_misses 606346 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 519644737 # DTB read accesses
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system.cpu.dtb.write_hits 282491025 # DTB write hits
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system.cpu.dtb.write_misses 50159 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 282541184 # DTB write accesses
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system.cpu.dtb.data_hits 801529416 # DTB hits
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system.cpu.dtb.data_misses 656505 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 802185921 # DTB accesses
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system.cpu.itb.fetch_hits 390623308 # ITB hits
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system.cpu.itb.fetch_misses 546 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 390623854 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 39 # Number of system calls
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system.cpu.numCycles 1252029901 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 405523870 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 3256215701 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 388875863 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 314307287 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 626203619 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 155794648 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 73991596 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 6471 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 390623308 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 10992432 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1235766511 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.634976 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.141364 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 609562892 49.33% 49.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 56929322 4.61% 53.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 42752934 3.46% 57.39% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 71333026 5.77% 63.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 128895698 10.43% 73.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 44916877 3.63% 77.23% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 41222080 3.34% 80.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 8947680 0.72% 81.29% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 231206002 18.71% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1235766511 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.310596 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.600749 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 434050234 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 59825791 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 602225660 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 9636107 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 130028719 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 31692009 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 12420 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3180730731 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 46427 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 130028719 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 463334620 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 24461750 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 27280 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 582229724 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 35684418 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3082031269 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 15345 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 29415634 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 2044995723 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3566316890 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3445638932 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 120677958 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 660026653 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 110158163 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 738560803 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 349770872 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 68005426 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 8800641 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2612267018 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2153832750 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 17944057 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 789157528 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 720017007 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1235766511 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.742912 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.802932 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 442318037 35.79% 35.79% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 194738197 15.76% 51.55% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 250284254 20.25% 71.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 121277806 9.81% 81.62% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 105807762 8.56% 90.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 77171137 6.24% 96.43% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 25347258 2.05% 98.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 17054134 1.38% 99.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1767926 0.14% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1235766511 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 1146289 3.17% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 25061435 69.20% 72.37% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 10007223 27.63% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1231694482 57.19% 57.19% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 17093 0.00% 57.19% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.19% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 27851386 1.29% 58.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 586233325 27.22% 86.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 292574368 13.58% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2153832750 # Type of FU issued
|
|
system.cpu.iq.rate 1.720273 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 36214947 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.016814 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5446489367 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 3313484734 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1984683423 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 151101648 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 88013502 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 73610007 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2112595001 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 77449944 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 62149579 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 227490777 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 22685 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 76128 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 138975976 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2362 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 130028719 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 10422536 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 524259 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2975772151 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 731348 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 738560803 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 349770872 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 195346 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 76128 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 25258103 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 28541 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 25286644 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2060237153 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 519644898 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 93595597 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 363505042 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 802186536 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 277071948 # Number of branches executed
|
|
system.cpu.iew.exec_stores 282541638 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.645518 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2060115451 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2058293430 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1179460731 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1750814151 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.643965 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.673664 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 949829893 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 25252672 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1105737792 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.816875 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.519271 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 488711252 44.20% 44.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 226575390 20.49% 64.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 120398789 10.89% 75.58% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 59423757 5.37% 80.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 48998760 4.43% 85.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 24145631 2.18% 87.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 18552721 1.68% 89.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 16148092 1.46% 90.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 102783400 9.30% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1105737792 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 721864922 # Number of memory references committed
|
|
system.cpu.commit.loads 511070026 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 266706457 # Number of branches committed
|
|
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 102783400 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3956135479 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6047665736 # The number of ROB writes
|
|
system.cpu.timesIdled 331504 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 16263390 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.686780 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.686780 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.456070 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.456070 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2621566555 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1491832809 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 78811406 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 52661103 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 8325 # number of replacements
|
|
system.cpu.icache.tagsinuse 1657.564105 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 390610507 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 38917.057587 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1657.564105 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.809357 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.809357 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 390610507 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 390610507 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 390610507 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 390610507 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 390610507 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 390610507 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 12801 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 12801 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 12801 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 12801 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 12801 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 12801 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 308797999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 308797999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 308797999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 308797999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 308797999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 308797999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 390623308 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 390623308 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 390623308 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 390623308 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 390623308 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 390623308 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24122.959066 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 24122.959066 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24122.959066 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 24122.959066 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24122.959066 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 24122.959066 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1026 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 85.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2763 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2763 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2763 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2763 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2763 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10038 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 10038 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 10038 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 10038 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 10038 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 10038 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233558499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 233558499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233558499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 233558499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233558499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 233558499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000026 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23267.433652 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23267.433652 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23267.433652 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 23267.433652 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23267.433652 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 23267.433652 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 443343 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 32701.945922 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1090021 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 476079 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 2.289580 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 1310.047547 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 33.839791 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31358.058585 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.039979 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001033 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.956972 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.997984 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 7288 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1053694 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1060982 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 95989 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 95989 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 7288 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1058482 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1065770 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 7288 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1058482 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1065770 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2750 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 406518 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 409268 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2750 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 473372 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 476122 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2750 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 473372 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 476122 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 150625500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28617502500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 28768128000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776521500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3776521500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 150625500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 32394024000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 32544649500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 150625500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 32394024000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 32544649500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10038 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460212 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1470250 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 95989 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 95989 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 71642 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 71642 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 10038 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1531854 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1541892 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 10038 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1531854 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1541892 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.273959 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278397 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.278366 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933168 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.933168 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.273959 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.309019 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.308791 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.273959 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.309019 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.308791 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54772.909091 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70396.642953 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70291.662187 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56489.088162 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56489.088162 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54772.909091 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68432.488614 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68353.593197 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54772.909091 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68432.488614 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68353.593197 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66908 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2750 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406518 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 409268 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2750 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 473372 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 476122 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2750 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 473372 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 476122 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116465465 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23520724104 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23637189569 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2970386425 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2970386425 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116465465 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26491110529 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 26607575994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116465465 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26491110529 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 26607575994 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273959 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278397 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278366 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273959 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309019 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.308791 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273959 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309019 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.308791 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42351.078182 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57858.997889 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57754.795315 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44430.945418 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44430.945418 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42351.078182 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55962.563331 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55883.945699 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42351.078182 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55962.563331 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55883.945699 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1527758 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.851524 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 664689576 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1531854 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 433.911832 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 314426000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.851524 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999720 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999720 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 454956433 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 454956433 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 209733120 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 209733120 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 664689553 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 664689553 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 664689553 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 664689553 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1925751 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1925751 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1061776 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1061776 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2987527 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65916980500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 65916980500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 35408599379 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 35408599379 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 101325579879 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 101325579879 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 101325579879 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 101325579879 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 456882184 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 456882184 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 23 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 23 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 667677080 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 667677080 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 667677080 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 667677080 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004215 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004215 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.004475 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.004475 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.004475 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.004475 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34229.233426 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 34229.233426 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33348.464628 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 33348.464628 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 33916.205570 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 33916.205570 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 13719 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 382 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.913613 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 95989 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465539 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 465539 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990134 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 990134 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1455673 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1455673 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1455673 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1455673 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460212 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1460212 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1531854 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1531854 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1531854 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1531854 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40615263000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 40615263000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3896657000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3896657000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44511920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 44511920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44511920000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 44511920000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003196 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003196 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002294 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002294 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27814.634450 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27814.634450 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54390.678652 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54390.678652 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|