7be58fd5f4
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
106 lines
3 KiB
C++
106 lines
3 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's 8254x line of gigabit ethernet controllers.
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*/
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#ifndef __DEV_I8254XGBE_HH__
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#define __DEV_I8254XGBE_HH__
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#include "base/inet.hh"
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#include "base/statistics.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/i8254xGBe_defs.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "sim/eventq.hh"
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class IGbEInt;
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class IGbE : public PciDev
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{
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private:
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IGbEInt *etherInt;
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iGbReg::Regs regs;
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int eeOpBits, eeAddrBits, eeDataBits;
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uint8_t eeOpcode, eeAddr;
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uint16_t flash[iGbReg::EEPROM_SIZE];
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public:
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struct Params : public PciDev::Params
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{
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;
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};
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IGbE(Params *params);
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~IGbE() {;}
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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virtual Tick writeConfig(PacketPtr pkt);
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bool ethRxPkt(EthPacketPtr packet);
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void ethTxDone();
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void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
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const Params *params() const {return (const Params *)_params; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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class IGbEInt : public EtherInt
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{
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private:
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IGbE *dev;
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public:
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IGbEInt(const std::string &name, IGbE *d)
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: EtherInt(name), dev(d)
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{ dev->setEthInt(this); }
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virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
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virtual void sendDone() { dev->ethTxDone(); }
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};
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#endif //__DEV_I8254XGBE_HH__
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