gem5/cpu
Kevin Lim 21df09cf7a Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
    Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
    Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
    Fixes for store conditionals.  Use an additional lock addr list to make sure that the access is valid.  I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
    Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
    Also support the new Checker.
cpu/ozone/cpu_builder.cc:
    Add parameter for maxOutstandingMemOps so it can be set through the config.
    Also add in the checker.  Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
    Add support for the checker.  For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type.  It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.

    Support switching out/taking over from other CPUs.

    Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
    Add ability for instructions to wait on memory instructions in addition to source register instructions.  This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
    Support waiting on memory operations.
    Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
    Support switching out.
    Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
    Support switching out.  Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
    Add checker in.
    Support switching out.
    Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
    Lots of changes to get things to work right.
    Faults, traps, interrupts all wait until all stores have written back (important).
    Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
    Support switching out.
    Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
    Support switching out.
    Also use store writeback events in all cases, not just dcache misses.
    Support the checker CPU.  Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
    Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
    Add max outstanding mem ops, checker.

--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-11 19:18:36 -04:00
..
memtest Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
o3 Small fixes to O3 model. 2006-05-11 15:39:02 -04:00
ozone Fixes for ozone CPU to successfully boot and run linux. 2006-05-11 19:18:36 -04:00
simple Fixes for the sampler. 2006-05-03 15:54:36 -04:00
trace Made Addr a global type 2006-02-21 03:38:21 -05:00
base.cc Fixes to allow the ExecContext to be used for profiling. 2006-03-07 22:21:39 -05:00
base.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
base_dyn_inst.cc Separate out result being ready and the instruction being complete. 2006-05-11 14:12:34 -04:00
base_dyn_inst.hh Fixes for ozone CPU to successfully boot and run linux. 2006-05-11 19:18:36 -04:00
cpu_exec_context.cc Set memory properly. 2006-05-11 15:19:48 -04:00
cpu_exec_context.hh Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
cpu_models.py Updates for OzoneCPU. 2006-04-22 18:45:01 -04:00
exec_context.hh Remove unnecessary functions. 2006-04-22 18:49:52 -04:00
exetrace.cc Allow the switching on and off of PC symbols for tracing. 2006-04-24 16:56:24 -04:00
exetrace.hh Allow the switching on and off of PC symbols for tracing. 2006-04-24 16:56:24 -04:00
inst_seq.hh Include option for disabling PC symbols. 2006-04-24 17:11:31 -04:00
intr_control.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
intr_control.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
profile.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
profile.hh Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
quiesce_event.cc Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
quiesce_event.hh Move quiesce event to its own class. 2006-04-22 18:11:54 -04:00
SConscript Include new OzoneCPU files 2006-04-22 19:17:05 -04:00
smt.hh Many files: 2005-06-05 05:16:00 -04:00
static_inst.cc Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
static_inst.hh Updates for OzoneCPU. 2006-04-22 19:10:39 -04:00
thread_state.hh Updates for O3 model. 2006-04-22 18:26:48 -04:00