805 lines
30 KiB
JSON
805 lines
30 KiB
JSON
{
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"name": null,
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"sim_quantum": 0,
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"system": {
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"membus": {
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"slave": {
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"peer": [
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"system.system_port",
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"system.l2c.mem_side"
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],
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"role": "SLAVE"
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},
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"name": "membus",
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"header_cycles": 1,
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"width": 8,
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"master": {
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"peer": [
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"system.physmem.port"
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],
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"role": "MASTER"
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},
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"cxx_class": "CoherentBus",
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"path": "system.membus",
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"type": "CoherentBus",
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"use_default_range": false
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},
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"l2c": {
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"assoc": 8,
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"mem_side": {
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"peer": "system.membus.slave[1]",
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"role": "MASTER"
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},
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"cpu_side": {
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"peer": "system.toL2Bus.master[0]",
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"role": "SLAVE"
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},
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"name": "l2c",
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},
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"name": "voltage_domain",
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},
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"physmem": {
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"name": "physmem",
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"cxx_class": "SimpleMemory",
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"path": "system.physmem",
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"port": {
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"peer": "system.membus.master[0]",
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"role": "SLAVE"
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},
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},
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"path": "system.clk_domain",
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"type": "SrcClockDomain"
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},
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"toL2Bus": {
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"slave": {
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"peer": [
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"system.cpu0.icache.mem_side",
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"system.cpu0.dcache.mem_side",
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"system.cpu1.icache.mem_side",
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"system.cpu1.dcache.mem_side",
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"system.cpu2.icache.mem_side",
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"system.cpu2.dcache.mem_side",
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"system.cpu3.icache.mem_side",
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"system.cpu3.dcache.mem_side"
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],
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"role": "SLAVE"
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},
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"name": "toL2Bus",
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"master": {
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],
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"role": "MASTER"
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},
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},
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"type": "System",
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"path": "system",
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"cxx_class": "SrcClockDomain",
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"path": "system.cpu_clk_domain",
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"type": "SrcClockDomain"
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},
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"mem_mode": "timing",
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"name": "system",
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"system_port": {
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"peer": "system.membus.slave[0]",
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"role": "MASTER"
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},
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"cpu": [
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{
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"size": 48
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},
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"peer": "system.toL2Bus.slave[1]",
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"role": "MASTER"
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},
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"cpu_side": {
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"peer": "system.cpu0.dcache_port",
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},
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"name": "dcache",
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"size": 32768
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},
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"cxx_class": "BaseCache",
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"path": "system.cpu0.dcache",
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"write_buffers": 8,
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"type": "BaseCache",
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"size": 32768
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},
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"type": "TimingSimpleCPU",
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},
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},
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{
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"name": "cpu0",
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},
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}
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{
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},
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},
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},
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},
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{
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}
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],
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{
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"type": "EioProcess"
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}
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],
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"name": "cpu1",
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},
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"peer": "system.cpu1.dcache.cpu_side",
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"role": "MASTER"
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},
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"path": "system.cpu1.tracer",
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"type": "ExeTracer",
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"name": "tracer",
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"cxx_class": "Trace::ExeTracer"
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}
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},
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{
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"do_statistics_insts": true,
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"itb": {
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"name": "itb",
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"cxx_class": "AlphaISA::TLB",
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"path": "system.cpu2.itb",
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"type": "AlphaTLB",
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"size": 48
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},
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"dcache": {
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"mem_side": {
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"peer": "system.toL2Bus.slave[5]",
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"role": "MASTER"
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},
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"cpu_side": {
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"peer": "system.cpu2.dcache_port",
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"role": "SLAVE"
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},
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"name": "dcache",
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"tags": {
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"cxx_class": "LRU",
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"size": 32768
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},
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"is_top_level": true,
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"sequential_access": false,
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"max_miss_count": 0,
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"eventq_index": 0,
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"prefetch_on_access": false,
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"cxx_class": "BaseCache",
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"path": "system.cpu2.dcache",
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"write_buffers": 8,
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"two_queue": false,
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"type": "BaseCache",
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"size": 32768
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},
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"do_checkpoint_insts": true,
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"cxx_class": "TimingSimpleCPU",
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},
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}
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}
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],
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}
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},
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{
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},
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},
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},
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},
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},
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},
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"type": "AlphaInterrupts",
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"name": "interrupts",
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},
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"path": "system.cpu3",
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{
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"type": "AlphaISA",
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}
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],
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{
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"type": "EioProcess"
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}
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],
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"name": "cpu3",
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},
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"role": "MASTER"
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},
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"path": "system.cpu3.tracer",
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"name": "tracer",
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}
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}
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],
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},
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"cxx_class": "Root",
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|
"path": "root",
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|
"time_sync_enable": false,
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"type": "Root",
|
|
"full_system": false
|
|
} |