20e9a90edc
which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
165 lines
5.6 KiB
C++
165 lines
5.6 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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/**
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* Static instruction class for unimplemented instructions that
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* cause simulator termination. Note that these are recognized
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* (legal) instructions that the simulator does not support; the
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* 'Unknown' class is used for unrecognized/illegal instructions.
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* This is a leaf class.
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*/
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class FailUnimplemented : public MipsStaticInst
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{
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public:
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/// Constructor
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FailUnimplemented(const char *_mnemonic, MachInst _machInst)
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: MipsStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for unimplemented instructions that cause a warning
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* to be printed (but do not terminate simulation). This
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* implementation is a little screwy in that it will print a
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* warning for each instance of a particular unimplemented machine
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* instruction, not just for each unimplemented opcode. Should
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* probably make the 'warned' flag a static member of the derived
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* class.
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*/
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class WarnUnimplemented : public MipsStaticInst
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{
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private:
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/// Have we warned on this instruction yet?
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mutable bool warned;
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public:
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/// Constructor
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WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
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: MipsStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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FailUnimplemented::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)", mnemonic);
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}
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std::string
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WarnUnimplemented::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return csprintf("%-10s", mnemonic);
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#else
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return csprintf("%-10s (unimplemented)", mnemonic);
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#endif
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}
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}};
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output exec {{
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Fault
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FailUnimplemented::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("attempt to execute unimplemented instruction '%s' "
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"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
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return UnimplementedOpcodeFault;
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}
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Fault
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WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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if (!warned) {
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warn("instruction '%s' unimplemented\n", mnemonic);
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warned = true;
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}
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return NoFault;
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}
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}};
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def format FailUnimpl() {{
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iop = InstObjParams(name, 'FailUnimplemented')
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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}};
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def format WarnUnimpl() {{
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iop = InstObjParams(name, 'WarnUnimplemented')
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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}};
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output header {{
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/**
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* Static instruction class for unknown (illegal) instructions.
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* These cause simulator termination if they are executed in a
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* non-speculative mode. This is a leaf class.
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*/
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class Unknown : public MipsStaticInst
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{
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public:
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/// Constructor
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Unknown(MachInst _machInst)
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: MipsStaticInst("unknown", _machInst, No_OpClass)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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%(BasicExecDeclare)s
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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