34260bbf0d
base/socket.cc:
Make panic print a more worthwhile message
dev/tsunami.hh:
Change max number of tsunami cpus to be 64
dev/tsunamireg.h:
Add new registers and register blocks for 64 cpu tsunami
--HG--
extra : convert_revision : 3ceaaa998518ded8613bc64edc04cb9120fd3d15
570 lines
19 KiB
C++
570 lines
19 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Emulation of the Tsunami CChip CSRs
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "cpu/intr_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
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MemoryController *mmu, HierParams *hier, Bus* bus,
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Tick pio_latency)
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: PioDevice(name), addr(a), tsunami(t)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiCChip::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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}
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drir = 0;
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ipint = 0;
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itint = 0;
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for (int x = 0; x < Tsunami::Max_CPUs; x++)
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{
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dim[x] = 0;
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dir[x] = 0;
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}
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//Put back pointer in tsunami
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tsunami->cchip = this;
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}
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Fault
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TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
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Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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ExecContext *xc = req->xc;
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switch (req->size) {
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case sizeof(uint64_t):
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if (daddr & TSDEV_CC_BDIMS)
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{
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*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
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return No_Fault;
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}
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if (daddr & TSDEV_CC_BDIRS)
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{
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*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
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return No_Fault;
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}
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switch(regnum) {
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case TSDEV_CC_CSR:
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*(uint64_t*)data = 0x0;
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR not implemeted\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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*(uint64_t*)data = (ipint << 8) & 0xF |
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(itint << 4) & 0xF |
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(xc->cpu_id & 0x3);
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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*(uint64_t*)data = 0;
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return No_Fault;
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case TSDEV_CC_DIM0:
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*(uint64_t*)data = dim[0];
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return No_Fault;
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case TSDEV_CC_DIM1:
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*(uint64_t*)data = dim[1];
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return No_Fault;
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case TSDEV_CC_DIM2:
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*(uint64_t*)data = dim[2];
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return No_Fault;
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case TSDEV_CC_DIM3:
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*(uint64_t*)data = dim[3];
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return No_Fault;
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case TSDEV_CC_DIR0:
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*(uint64_t*)data = dir[0];
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return No_Fault;
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case TSDEV_CC_DIR1:
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*(uint64_t*)data = dir[1];
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return No_Fault;
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case TSDEV_CC_DIR2:
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*(uint64_t*)data = dir[2];
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return No_Fault;
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case TSDEV_CC_DIR3:
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*(uint64_t*)data = dir[3];
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return No_Fault;
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case TSDEV_CC_DRIR:
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*(uint64_t*)data = drir;
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return No_Fault;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN not implemented\n");
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return No_Fault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx not implemented\n");
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return No_Fault;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx not implemented\n");
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return No_Fault;
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case TSDEV_CC_IPIR:
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*(uint64_t*)data = ipint;
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return No_Fault;
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case TSDEV_CC_ITIR:
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*(uint64_t*)data = itint;
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return No_Fault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
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return No_Fault;
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}
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Fault
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TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
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req->vaddr, *(uint64_t*)data, req->size);
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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bool supportedWrite = false;
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switch (req->size) {
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case sizeof(uint64_t):
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if (daddr & TSDEV_CC_BDIMS)
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{
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int number = (daddr >> 4) & 0x3F;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = *(uint64_t*)data;
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dir[number] = dim[number] & drir;
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for(int x = 0; x < Tsunami::Max_CPUs; x++)
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{
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bitvector = ULL(1) << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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// The bit is now set and it wasn't before (set)
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if((dim[number] & bitvector) && (dir[number] & bitvector))
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{
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in posting dir"
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" interrupt to cpu %d\n", number);
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}
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in clear"
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" dir interrupt to cpu %d\n", number);
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}
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}
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}
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return No_Fault;
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}
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switch(regnum) {
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case TSDEV_CC_CSR:
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panic("TSDEV_CC_CSR write\n");
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR write not implemented\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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uint64_t ipreq;
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ipreq = (*(uint64_t*)data >> 12) & 0xF;
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//If it is bit 12-15, this is an IPI post
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if (ipreq) {
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reqIPI(ipreq);
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supportedWrite = true;
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}
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//If it is bit 8-11, this is an IPI clear
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uint64_t ipintr;
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ipintr = (*(uint64_t*)data >> 8) & 0xF;
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if (ipintr) {
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clearIPI(ipintr);
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supportedWrite = true;
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}
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//If it is the 4-7th bit, clear the RTC interrupt
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uint64_t itintr;
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itintr = (*(uint64_t*)data >> 4) & 0xF;
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if (itintr) {
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clearITI(itintr);
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supportedWrite = true;
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}
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// ignore NXMs
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if (*(uint64_t*)data & 0x10000000)
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supportedWrite = true;
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if(!supportedWrite)
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panic("TSDEV_CC_MISC write not implemented\n");
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx write not implemeted\n");
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return No_Fault;
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case TSDEV_CC_DIM0:
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case TSDEV_CC_DIM1:
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case TSDEV_CC_DIM2:
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case TSDEV_CC_DIM3:
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int number;
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if(regnum == TSDEV_CC_DIM0)
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number = 0;
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else if(regnum == TSDEV_CC_DIM1)
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number = 1;
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else if(regnum == TSDEV_CC_DIM2)
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number = 2;
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else
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number = 3;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = *(uint64_t*)data;
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dir[number] = dim[number] & drir;
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for(int x = 0; x < 64; x++)
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{
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bitvector = ULL(1) << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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// The bit is now set and it wasn't before (set)
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if((dim[number] & bitvector) && (dir[number] & bitvector))
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{
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
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}
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in clear"
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" dir interrupt to cpu %d\n",
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x);
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}
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}
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}
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return No_Fault;
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case TSDEV_CC_DIR0:
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case TSDEV_CC_DIR1:
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case TSDEV_CC_DIR2:
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case TSDEV_CC_DIR3:
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panic("TSDEV_CC_DIR write not implemented\n");
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case TSDEV_CC_DRIR:
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panic("TSDEV_CC_DRIR write not implemented\n");
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN write not implemented\n");
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx write not implemented\n");
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx write not implemented\n");
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case TSDEV_CC_IPIR:
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clearIPI(*(uint64_t*)data);
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return No_Fault;
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case TSDEV_CC_ITIR:
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clearITI(*(uint64_t*)data);
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return No_Fault;
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case TSDEV_CC_IPIQ:
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reqIPI(*(uint64_t*)data);
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return No_Fault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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}
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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void
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TsunamiCChip::clearIPI(uint64_t ipintr)
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{
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int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(numcpus <= Tsunami::Max_CPUs);
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if (ipintr) {
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for (int cpunum=0; cpunum < numcpus; cpunum++) {
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// Check each cpu bit
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uint64_t cpumask = ULL(1) << cpunum;
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if (ipintr & cpumask) {
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// Check if there is a pending ipi
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if (ipint & cpumask) {
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ipint &= ~cpumask;
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tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
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DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
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}
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else
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warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
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}
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}
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}
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else
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panic("Big IPI Clear, but not processors indicated\n");
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}
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void
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TsunamiCChip::clearITI(uint64_t itintr)
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{
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int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(numcpus <= Tsunami::Max_CPUs);
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if (itintr) {
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for (int i=0; i < numcpus; i++) {
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uint64_t cpumask = ULL(1) << i;
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if (itintr & cpumask & itint) {
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tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
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itint &= ~cpumask;
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DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
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}
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}
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}
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else
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panic("Big ITI Clear, but not processors indicated\n");
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}
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void
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TsunamiCChip::reqIPI(uint64_t ipreq)
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{
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int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(numcpus <= Tsunami::Max_CPUs);
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if (ipreq) {
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for (int cpunum=0; cpunum < numcpus; cpunum++) {
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// Check each cpu bit
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uint64_t cpumask = ULL(1) << cpunum;
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if (ipreq & cpumask) {
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// Check if there is already an ipi (bits 8:11)
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if (!(ipint & cpumask)) {
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ipint |= cpumask;
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tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
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DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
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}
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else
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warn("post IPI for CPU=%d, but IPI already\n", cpunum);
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}
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}
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}
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else
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panic("Big IPI Request, but not processors indicated\n");
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}
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void
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TsunamiCChip::postRTC()
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{
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int size = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(size <= Tsunami::Max_CPUs);
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for (int i = 0; i < size; i++) {
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uint64_t cpumask = ULL(1) << i;
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if (!(cpumask & itint)) {
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itint |= cpumask;
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tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
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DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
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}
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}
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}
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void
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TsunamiCChip::postDRIR(uint32_t interrupt)
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{
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uint64_t bitvector = ULL(1) << interrupt;
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uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(size <= Tsunami::Max_CPUs);
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drir |= bitvector;
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for(int i=0; i < size; i++) {
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dir[i] = dim[i] & drir;
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if (dim[i] & bitvector) {
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tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
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DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
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"interrupt %d\n",i, interrupt);
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}
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}
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}
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void
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TsunamiCChip::clearDRIR(uint32_t interrupt)
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{
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uint64_t bitvector = ULL(1) << interrupt;
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uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
if (drir & bitvector)
|
|
{
|
|
drir &= ~bitvector;
|
|
for(int i=0; i < size; i++) {
|
|
if (dir[i] & bitvector) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
|
|
}
|
|
dir[i] = dim[i] & drir;
|
|
}
|
|
}
|
|
else
|
|
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
|
}
|
|
|
|
Tick
|
|
TsunamiCChip::cacheAccess(MemReqPtr &req)
|
|
{
|
|
return curTick + pioLatency;
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
SERIALIZE_SCALAR(ipint);
|
|
SERIALIZE_SCALAR(itint);
|
|
SERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_SCALAR(ipint);
|
|
UNSERIALIZE_SCALAR(itint);
|
|
UNSERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
SimObjectParam<Tsunami *> tsunami;
|
|
SimObjectParam<MemoryController *> mmu;
|
|
Param<Addr> addr;
|
|
SimObjectParam<Bus*> io_bus;
|
|
Param<Tick> pio_latency;
|
|
SimObjectParam<HierParams *> hier;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
INIT_PARAM(tsunami, "Tsunami"),
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
|
INIT_PARAM(addr, "Device Address"),
|
|
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
CREATE_SIM_OBJECT(TsunamiCChip)
|
|
{
|
|
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier,
|
|
io_bus, pio_latency);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|