Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * * |
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branch.isa | ||
decoder.isa | ||
fp.isa | ||
int.isa | ||
main.isa | ||
mem.isa | ||
opcdec.isa | ||
pal.isa | ||
unimp.isa | ||
unknown.isa | ||
util.isa |