149 lines
3.9 KiB
C++
149 lines
3.9 KiB
C++
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#include "mem/ruby/system/DMASequencer.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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/* SLICC generated types */
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#include "mem/protocol/SequencerMsg.hh"
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#include "mem/protocol/SequencerRequestType.hh"
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#include "mem/ruby/system/System.hh"
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//
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// Fix me: This code needs comments!
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//
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DMASequencer::DMASequencer(const Params *p)
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: RubyPort(p)
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{
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}
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void DMASequencer::init()
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{
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RubyPort::init();
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m_is_busy = false;
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m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
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}
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RequestStatus DMASequencer::makeRequest(const RubyRequest & request)
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{
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uint64_t paddr = request.paddr;
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uint8_t* data = request.data;
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int len = request.len;
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bool write = false;
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switch(request.type) {
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case RubyRequestType_LD:
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write = false;
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break;
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case RubyRequestType_ST:
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write = true;
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break;
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case RubyRequestType_NULL:
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case RubyRequestType_IFETCH:
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case RubyRequestType_Locked_Read:
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case RubyRequestType_Locked_Write:
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case RubyRequestType_RMW_Read:
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case RubyRequestType_RMW_Write:
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case RubyRequestType_NUM:
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panic("DMASequencer::makeRequest does not support the RubyRequestType");
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return RequestStatus_NULL;
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}
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assert(!m_is_busy); // only support one outstanding DMA request
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m_is_busy = true;
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active_request.start_paddr = paddr;
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active_request.write = write;
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active_request.data = data;
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active_request.len = len;
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active_request.bytes_completed = 0;
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active_request.bytes_issued = 0;
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active_request.pkt = request.pkt;
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SequencerMsg msg;
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msg.getPhysicalAddress() = Address(paddr);
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msg.getLineAddress() = line_address(msg.getPhysicalAddress());
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msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
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int offset = paddr & m_data_block_mask;
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msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
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len :
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RubySystem::getBlockSizeBytes() - offset;
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if (write) {
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msg.getDataBlk().setData(data, offset, msg.getLen());
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}
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assert(m_mandatory_q_ptr != NULL);
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m_mandatory_q_ptr->enqueue(msg);
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active_request.bytes_issued += msg.getLen();
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return RequestStatus_Issued;
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}
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void DMASequencer::issueNext()
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{
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assert(m_is_busy == true);
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active_request.bytes_completed = active_request.bytes_issued;
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if (active_request.len == active_request.bytes_completed) {
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ruby_hit_callback(active_request.pkt);
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m_is_busy = false;
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return;
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}
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SequencerMsg msg;
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msg.getPhysicalAddress() = Address(active_request.start_paddr +
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active_request.bytes_completed);
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assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
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msg.getLineAddress() = line_address(msg.getPhysicalAddress());
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msg.getType() = (active_request.write ? SequencerRequestType_ST :
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SequencerRequestType_LD);
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msg.getLen() = (active_request.len -
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active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
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active_request.len - active_request.bytes_completed :
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RubySystem::getBlockSizeBytes());
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if (active_request.write) {
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msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
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0, msg.getLen());
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msg.getType() = SequencerRequestType_ST;
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} else {
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msg.getType() = SequencerRequestType_LD;
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}
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assert(m_mandatory_q_ptr != NULL);
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m_mandatory_q_ptr->enqueue(msg);
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active_request.bytes_issued += msg.getLen();
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}
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void DMASequencer::dataCallback(const DataBlock & dblk)
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{
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assert(m_is_busy == true);
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int len = active_request.bytes_issued - active_request.bytes_completed;
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int offset = 0;
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if (active_request.bytes_completed == 0)
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offset = active_request.start_paddr & m_data_block_mask;
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assert( active_request.write == false );
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memcpy(&active_request.data[active_request.bytes_completed],
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dblk.getData(offset, len), len);
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issueNext();
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}
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void DMASequencer::ackCallback()
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{
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issueNext();
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}
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void DMASequencer::printConfig(ostream & out)
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{
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}
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DMASequencer *
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DMASequencerParams::create()
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{
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return new DMASequencer(this);
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}
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