33b28fde7a
This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported.
105 lines
4.6 KiB
Text
105 lines
4.6 KiB
Text
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*
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*/
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// CoherenceRequestType
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enumeration(CoherenceRequestType, desc="...") {
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GETX, desc="Get eXclusive";
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GETS, desc="Get Shared";
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PUTX, desc="Put eXclusive";
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PUTO, desc="Put Owned";
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PUTO_SHARERS, desc="Put Owned, but sharers exist so don't remove from sharers list";
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PUTS, desc="Put Shared";
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WB_ACK, desc="Writeback ack";
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WB_ACK_DATA, desc="Writeback ack";
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WB_NACK, desc="Writeback neg. ack";
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INV, desc="Invalidation";
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DMA_READ, desc="DMA Read";
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DMA_WRITE, desc="DMA Write";
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}
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// CoherenceResponseType
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enumeration(CoherenceResponseType, desc="...") {
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ACK, desc="ACKnowledgment, responder doesn't have a copy";
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DATA, desc="Data";
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DATA_EXCLUSIVE, desc="Data, no processor has a copy";
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UNBLOCK, desc="Unblock";
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UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M";
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WRITEBACK_CLEAN_DATA, desc="Clean writeback (contains data)";
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WRITEBACK_CLEAN_ACK, desc="Clean writeback (contains no data)";
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WRITEBACK_DIRTY_DATA, desc="Dirty writeback (contains data)";
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DMA_ACK, desc="Ack that a DMA write completed";
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}
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// TriggerType
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enumeration(TriggerType, desc="...") {
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ALL_ACKS, desc="See corresponding event";
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}
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// TriggerMsg
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structure(TriggerMsg, desc="...", interface="Message") {
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Address Address, desc="Physical address for this request";
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TriggerType Type, desc="Type of trigger";
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}
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// RequestMsg (and also forwarded requests)
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structure(RequestMsg, desc="...", interface="NetworkMessage") {
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Address Address, desc="Physical address for this request";
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int Len, desc="Length of Request";
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CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
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MachineID Requestor, desc="Node who initiated the request";
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MachineType RequestorMachine, desc="type of component";
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NetDest Destination, desc="Multicast destination mask";
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DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)";
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int Acks, desc="How many acks to expect";
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MessageSizeType MessageSize, desc="size category of the message";
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AccessModeType AccessMode, desc="user/supervisor access type";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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}
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// ResponseMsg (and also unblock requests)
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structure(ResponseMsg, desc="...", interface="NetworkMessage") {
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Address Address, desc="Physical address for this request";
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CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
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MachineID Sender, desc="Node who sent the data";
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MachineType SenderMachine, desc="type of component sending msg";
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NetDest Destination, desc="Node to whom the data is sent";
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DataBlock DataBlk, desc="data for the cache line";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int Acks, desc="How many acks to expect";
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MessageSizeType MessageSize, desc="size category of the message";
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}
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