347 lines
11 KiB
C++
347 lines
11 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_MISCREGS_HH__
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#define __ARCH_ARM_MISCREGS_HH__
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#include "base/bitunion.hh"
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namespace ArmISA
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{
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enum ConditionCode {
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COND_EQ = 0,
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COND_NE, // 1
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COND_CS, // 2
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COND_CC, // 3
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COND_MI, // 4
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COND_PL, // 5
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COND_VS, // 6
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COND_VC, // 7
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COND_HI, // 8
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COND_LS, // 9
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COND_GE, // 10
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COND_LT, // 11
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COND_GT, // 12
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COND_LE, // 13
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COND_AL, // 14
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COND_UC // 15
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};
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enum MiscRegIndex {
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MISCREG_CPSR = 0,
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MISCREG_SPSR,
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MISCREG_SPSR_FIQ,
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MISCREG_SPSR_IRQ,
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MISCREG_SPSR_SVC,
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MISCREG_SPSR_MON,
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MISCREG_SPSR_UND,
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MISCREG_SPSR_ABT,
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MISCREG_FPSR,
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MISCREG_FPSID,
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MISCREG_FPSCR,
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MISCREG_FPEXC,
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MISCREG_MVFR0,
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MISCREG_MVFR1,
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MISCREG_SEV_MAILBOX,
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// CP15 registers
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MISCREG_CP15_START,
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MISCREG_SCTLR = MISCREG_CP15_START,
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MISCREG_DCCISW,
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MISCREG_DCCIMVAC,
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MISCREG_DCCMVAC,
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MISCREG_CONTEXTIDR,
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MISCREG_TPIDRURW,
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MISCREG_TPIDRURO,
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MISCREG_TPIDRPRW,
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MISCREG_CP15ISB,
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MISCREG_CP15DSB,
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MISCREG_CP15DMB,
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MISCREG_CPACR,
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MISCREG_CLIDR,
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MISCREG_CCSIDR,
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MISCREG_CSSELR,
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MISCREG_ICIALLUIS,
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MISCREG_ICIALLU,
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MISCREG_ICIMVAU,
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MISCREG_BPIMVA,
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MISCREG_BPIALLIS,
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MISCREG_BPIALL,
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MISCREG_MIDR,
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MISCREG_TTBR0,
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MISCREG_TTBR1,
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MISCREG_TLBTR,
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MISCREG_DACR,
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MISCREG_TLBIALLIS,
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MISCREG_TLBIMVAIS,
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MISCREG_TLBIASIDIS,
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MISCREG_TLBIMVAAIS,
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MISCREG_ITLBIALL,
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MISCREG_ITLBIMVA,
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MISCREG_ITLBIASID,
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MISCREG_DTLBIALL,
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MISCREG_DTLBIMVA,
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MISCREG_DTLBIASID,
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MISCREG_TLBIALL,
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MISCREG_TLBIMVA,
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MISCREG_TLBIASID,
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MISCREG_TLBIMVAA,
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MISCREG_DFSR,
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MISCREG_IFSR,
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MISCREG_DFAR,
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MISCREG_IFAR,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_TCMTR,
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MISCREG_MPIDR,
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MISCREG_ID_PFR0,
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MISCREG_ID_PFR1,
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MISCREG_ID_DFR0,
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MISCREG_ID_AFR0,
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MISCREG_ID_MMFR0,
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MISCREG_ID_MMFR1,
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MISCREG_ID_MMFR2,
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MISCREG_ID_MMFR3,
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MISCREG_ID_ISAR0,
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MISCREG_ID_ISAR1,
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MISCREG_ID_ISAR2,
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MISCREG_ID_ISAR3,
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MISCREG_ID_ISAR4,
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MISCREG_ID_ISAR5,
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MISCREG_PAR,
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MISCREG_AIDR,
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MISCREG_ACTLR,
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MISCREG_ADFSR,
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MISCREG_AIFSR,
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MISCREG_DCIMVAC,
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MISCREG_DCISW,
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MISCREG_MCCSW,
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MISCREG_DCCMVAU,
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MISCREG_SCR,
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MISCREG_SDER,
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MISCREG_NSACR,
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MISCREG_TTBCR,
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MISCREG_V2PCWPR,
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MISCREG_V2PCWPW,
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MISCREG_V2PCWUR,
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MISCREG_V2PCWUW,
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MISCREG_V2POWPR,
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MISCREG_V2POWPW,
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MISCREG_V2POWUR,
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MISCREG_V2POWUW,
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MISCREG_PRRR,
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MISCREG_NMRR,
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MISCREG_VBAR,
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MISCREG_MVBAR,
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MISCREG_ISR,
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MISCREG_FCEIDR,
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MISCREG_CP15_END,
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// Dummy indices
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MISCREG_NOP = MISCREG_CP15_END,
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MISCREG_RAZ,
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NUM_MISCREGS
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};
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MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
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unsigned crm, unsigned opc2);
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const char * const miscRegName[NUM_MISCREGS] = {
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"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
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"spsr_mon", "spsr_und", "spsr_abt",
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"fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
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"sev_mailbox",
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"sctlr", "dccisw", "dccimvac", "dccmvac",
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"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
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"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
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"clidr", "ccsidr", "csselr",
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"icialluis", "iciallu", "icimvau",
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"bpimva", "bpiallis", "bpiall",
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"midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
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"tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
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"itlbiall", "itlbimva", "itlbiasid",
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"dtlbiall", "dtlbimva", "dtlbiasid",
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"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
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"dfsr", "ifsr", "dfar", "ifar",
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"ctr", "tcmtr", "mpidr",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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"par", "aidr", "actlr",
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"adfsr", "aifsr",
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"dcimvac", "dcisw", "mccsw",
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"dccmvau",
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"scr", "sder", "nsacr", "ttbcr",
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"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
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"v2powpr", "v2powpw", "v2powur", "v2powuw",
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"prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
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"nop", "raz"
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};
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BitUnion32(CPSR)
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Bitfield<31> n;
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Bitfield<30> z;
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Bitfield<29> c;
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Bitfield<28> v;
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Bitfield<27> q;
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Bitfield<26,25> it1;
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Bitfield<24> j;
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Bitfield<19, 16> ge;
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Bitfield<15,10> it2;
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Bitfield<9> e;
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Bitfield<8> a;
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Bitfield<7> i;
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Bitfield<6> f;
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Bitfield<5> t;
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Bitfield<4, 0> mode;
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EndBitUnion(CPSR)
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// This mask selects bits of the CPSR that actually go in the CondCodes
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// integer register to allow renaming.
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static const uint32_t CondCodesMask = 0xF80F0000;
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BitUnion32(SCTLR)
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Bitfield<31> ie; // Instruction endianness
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Bitfield<30> te; // Thumb Exception Enable
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Bitfield<29> afe; // Access flag enable
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Bitfield<28> tre; // TEX Remap bit
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Bitfield<27> nmfi;// Non-maskable fast interrupts enable
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Bitfield<25> ee; // Exception Endianness bit
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Bitfield<24> ve; // Interrupt vectors enable
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Bitfield<23> rao1;// Read as one
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Bitfield<22> u; // Alignment (now unused)
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Bitfield<21> fi; // Fast interrupts configuration enable
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Bitfield<19> dz; // Divide by Zero fault enable bit
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Bitfield<18> rao2;// Read as one
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Bitfield<17> br; // Background region bit
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Bitfield<16> rao3;// Read as one
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Bitfield<14> rr; // Round robin cache replacement
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Bitfield<13> v; // Base address for exception vectors
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Bitfield<12> i; // instruction cache enable
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Bitfield<11> z; // branch prediction enable bit
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Bitfield<10> sw; // Enable swp/swpb
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Bitfield<6,3> rao4;// Read as one
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Bitfield<7> b; // Endianness support (unused)
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Bitfield<2> c; // Cache enable bit
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Bitfield<1> a; // Alignment fault checking
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Bitfield<0> m; // MMU enable bit
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EndBitUnion(SCTLR)
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BitUnion32(CPACR)
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Bitfield<1, 0> cp0;
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Bitfield<3, 2> cp1;
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Bitfield<5, 4> cp2;
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Bitfield<7, 6> cp3;
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Bitfield<9, 8> cp4;
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Bitfield<11, 10> cp5;
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Bitfield<13, 12> cp6;
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Bitfield<15, 14> cp7;
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Bitfield<17, 16> cp8;
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Bitfield<19, 18> cp9;
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Bitfield<21, 20> cp10;
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Bitfield<23, 22> cp11;
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Bitfield<25, 24> cp12;
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Bitfield<27, 26> cp13;
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Bitfield<30> d32dis;
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Bitfield<31> asedis;
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EndBitUnion(CPACR)
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BitUnion32(FSR)
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Bitfield<3, 0> fsLow;
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Bitfield<7, 4> domain;
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Bitfield<10> fsHigh;
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Bitfield<11> wnr;
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Bitfield<12> ext;
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EndBitUnion(FSR)
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BitUnion32(FPSCR)
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Bitfield<0> ioc;
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Bitfield<1> dzc;
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Bitfield<2> ofc;
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Bitfield<3> ufc;
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Bitfield<4> ixc;
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Bitfield<7> idc;
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Bitfield<8> ioe;
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Bitfield<9> dze;
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Bitfield<10> ofe;
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Bitfield<11> ufe;
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Bitfield<12> ixe;
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Bitfield<15> ide;
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Bitfield<18, 16> len;
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Bitfield<21, 20> stride;
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Bitfield<23, 22> rMode;
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Bitfield<24> fz;
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Bitfield<25> dn;
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Bitfield<26> ahp;
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Bitfield<27> qc;
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Bitfield<28> v;
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Bitfield<29> c;
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Bitfield<30> z;
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Bitfield<31> n;
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EndBitUnion(FPSCR)
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BitUnion32(MVFR0)
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Bitfield<3, 0> advSimdRegisters;
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Bitfield<7, 4> singlePrecision;
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Bitfield<11, 8> doublePrecision;
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Bitfield<15, 12> vfpExceptionTrapping;
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Bitfield<19, 16> divide;
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Bitfield<23, 20> squareRoot;
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Bitfield<27, 24> shortVectors;
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Bitfield<31, 28> roundingModes;
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EndBitUnion(MVFR0)
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BitUnion32(MVFR1)
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Bitfield<3, 0> flushToZero;
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Bitfield<7, 4> defaultNaN;
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Bitfield<11, 8> advSimdLoadStore;
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Bitfield<15, 12> advSimdInteger;
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Bitfield<19, 16> advSimdSinglePrecision;
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Bitfield<23, 20> advSimdHalfPrecision;
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Bitfield<27, 24> vfpHalfPrecision;
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Bitfield<31, 28> raz;
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EndBitUnion(MVFR1)
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};
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#endif // __ARCH_ARM_MISCREGS_HH__
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