125 lines
3.2 KiB
C++
125 lines
3.2 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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/** @file
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* Implementation of PC platform.
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "arch/x86/x86_traits.hh"
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#include "dev/intel_8254_timer.hh"
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#include "cpu/intr_control.hh"
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#include "dev/simconsole.hh"
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#include "dev/x86/pc.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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PC::PC(const Params *p)
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: Platform(p), system(p->system)
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{
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southBridge = NULL;
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// set the back pointer from the system to myself
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system->platform = this;
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}
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void
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PC::init()
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{
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assert(southBridge);
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Intel8254Timer & timer = southBridge->pit.pit;
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//Timer 0, mode 2, no bcd, 16 bit count
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timer.writeControl(0x34);
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//Timer 0, latch command
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timer.writeControl(0x00);
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//Write a 16 bit count of 0
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timer.counter0.write(0);
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timer.counter0.write(0);
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}
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Tick
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PC::intrFrequency()
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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}
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void
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PC::postConsoleInt()
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{
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warn_once("Don't know what interrupt to post for console.\n");
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//panic("Need implementation\n");
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}
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void
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PC::clearConsoleInt()
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{
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warn_once("Don't know what interrupt to clear for console.\n");
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//panic("Need implementation\n");
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}
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void
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PC::postPciInt(int line)
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{
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panic("Need implementation\n");
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}
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void
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PC::clearPciInt(int line)
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{
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panic("Need implementation\n");
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}
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Addr
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PC::pciToDma(Addr pciAddr) const
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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}
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Addr
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PC::calcConfigAddr(int bus, int dev, int func)
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{
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assert(func < 8);
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assert(dev < 32);
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assert(bus == 0);
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return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
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}
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PC *
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PCParams::create()
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{
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return new PC(this);
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}
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