gem5/src/arch
Alexandru Dutu 1f539f13c3 mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
2014-11-23 18:01:09 -08:00
..
alpha mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
arm mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
generic kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
mips mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
null arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
power mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
sparc mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
x86 mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
isa_parser.py scons: Address issues related to gcc 4.9.1 2014-09-27 09:08:34 -04:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00