1c8dfd9254
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)
133 lines
4.7 KiB
Python
133 lines
4.7 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import sys
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Import('*')
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#################################################################
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#
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# ISA "switch header" generation.
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#
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# Auto-generate arch headers that include the right ISA-specific
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# header based on the setting of THE_ISA preprocessor variable.
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#
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#################################################################
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# List of headers to generate
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isa_switch_hdrs = Split('''
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arguments.hh
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faults.hh
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interrupts.hh
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isa_traits.hh
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kernel_stats.hh
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locked_mem.hh
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microcode_rom.hh
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mmaped_ipr.hh
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mt.hh
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process.hh
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predecoder.hh
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regfile.hh
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remote_gdb.hh
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stacktrace.hh
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tlb.hh
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types.hh
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utility.hh
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vtophys.hh
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''')
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# Set up this directory to support switching headers
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make_switching_dir('arch', isa_switch_hdrs, env)
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#################################################################
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#
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# Include architecture-specific files.
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#
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#################################################################
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#
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# Build a SCons scanner for ISA files
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#
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import SCons.Scanner
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isa_scanner = SCons.Scanner.Classic("ISAScan",
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[".isa", ".ISA"],
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"SRCDIR",
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r'^\s*##include\s+"([\w/.-]*)"')
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env.Append(SCANNERS = isa_scanner)
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#
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# Now create a Builder object that uses isa_parser.py to generate C++
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# output from the ISA description (*.isa) files.
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#
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# Convert to File node to fix path
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isa_parser = File('isa_parser.py')
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cpu_models_file = File('../cpu/cpu_models.py')
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# This sucks in the defintions of the CpuModel objects.
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execfile(cpu_models_file.srcnode().abspath)
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# Several files are generated from the ISA description.
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# We always get the basic decoder and header file.
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isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
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# We also get an execute file for each selected CPU model.
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isa_desc_gen_files += [CpuModel.dict[cpu].filename
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for cpu in env['CPU_MODELS']]
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# Also include the CheckerCPU as one of the models if it is being
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# enabled via command line.
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if env['USE_CHECKER']:
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isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
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# The emitter patches up the sources & targets to include the
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# autogenerated files as targets and isa parser itself as a source.
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def isa_desc_emitter(target, source, env):
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return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
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# Pieces are in place, so create the builder.
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python = sys.executable # use same Python binary used to run scons
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# Also include the CheckerCPU as one of the models if it is being
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# enabled via command line.
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if env['USE_CHECKER']:
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isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
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emitter = isa_desc_emitter)
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else:
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isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
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emitter = isa_desc_emitter)
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env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
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TraceFlag('IntRegs')
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TraceFlag('FloatRegs')
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TraceFlag('MiscRegs')
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CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
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