482 lines
18 KiB
Text
482 lines
18 KiB
Text
// Copyright (c) 2007 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// RegOp Microop templates
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//
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//////////////////////////////////////////////////////////////////////////
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def template MicroRegOpExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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if(%(cond_check)s)
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{
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%(code)s;
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%(flag_code)s;
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}
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else
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{
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%(else_code)s;
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}
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//Write the resulting state to the execution context
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroRegOpImmExecute {{
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Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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if(%(cond_check)s)
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{
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%(code)s;
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%(flag_code)s;
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}
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else
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{
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%(else_code)s;
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}
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//Write the resulting state to the execution context
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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void buildMe();
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext);
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroRegOpImmDeclare {{
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class %(class_name)sImm : public %(base_class)s
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{
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protected:
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void buildMe();
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public:
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%(class_name)sImm(ExtMachInst _machInst,
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext);
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%(class_name)sImm(ExtMachInst _machInst,
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const char * instMnem,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroRegOpConstructor {{
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inline void %(class_name)s::buildMe()
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{
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%(constructor)s;
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}
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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false, false, false, false,
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_src1, _src2, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _src2, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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}};
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def template MicroRegOpImmConstructor {{
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inline void %(class_name)sImm::buildMe()
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{
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%(constructor)s;
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}
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inline %(class_name)sImm::%(class_name)sImm(
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ExtMachInst machInst, const char * instMnem,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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false, false, false, false,
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_src1, _imm8, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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inline %(class_name)sImm::%(class_name)sImm(
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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uint8_t _dataSize, uint16_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _imm8, _dest, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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}};
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let {{
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class X86MicroMeta(type):
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def __new__(mcls, name, bases, dict):
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abstract = False
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if "abstract" in dict:
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abstract = dict['abstract']
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del dict['abstract']
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cls = type.__new__(mcls, name, bases, dict)
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if not abstract:
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allClasses[name] = cls
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return cls
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class XXX86Microop(object):
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__metaclass__ = X86MicroMeta
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abstract = True
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class RegOp(X86Microop):
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abstract = True
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def __init__(self, dest, src1, src2, flags, dataSize):
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self.dest = dest
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self.src1 = src1
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self.src2 = src2
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self.flags = flags
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self.dataSize = dataSize
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(src2)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "src2" : self.src2,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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class RegOpImm(X86Microop):
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abstract = True
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def __init__(self, dest, src1, imm8, flags, dataSize):
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self.dest = dest
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self.src1 = src1
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self.imm8 = imm8
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self.flags = flags
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self.dataSize = dataSize
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if flags is None:
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self.ext = 0
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else:
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if not isinstance(flags, (list, tuple)):
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raise Exception, "flags must be a list or tuple of flags"
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self.ext = " | ".join(flags)
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self.className += "Flags"
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(imm8)s, %(dest)s,
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%(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "imm8" : self.imm8,
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"dest" : self.dest,
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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}};
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let {{
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# Make these empty strings so that concatenating onto
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# them will always work.
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header_output = ""
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decoder_output = ""
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exec_output = ""
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# A function which builds the C++ classes that implement the microops
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def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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iop = InstObjParams(name, Name, base,
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{"code" : code,
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"flag_code" : flagCode,
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"cond_check" : condCheck,
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"else_code" : elseCode})
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header_output += MicroRegOpDeclare.subst(iop)
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decoder_output += MicroRegOpConstructor.subst(iop)
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exec_output += MicroRegOpExecute.subst(iop)
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checkCCFlagBits = "checkCondition(ccFlagBits)"
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genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);"
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# This creates a python representations of a microop which are a cross
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# product of reg/immediate and flag/no flag versions.
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def defineMicroRegOp(mnemonic, code, subtract = False, cc=False, elseCode=";"):
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Name = mnemonic
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name = mnemonic.lower()
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# Find op2 in each of the instruction definitions. Create two versions
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = matcher.sub("SrcReg2", code)
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immCode = matcher.sub("imm8", code)
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if subtract:
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secondSrc = "-op2, true"
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else:
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secondSrc = "op2"
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if not cc:
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flagCode = genCCFlagBits % secondSrc
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condCode = "true"
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else:
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flagCode = ""
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condCode = checkCCFlagBits
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regFlagCode = matcher.sub("SrcReg2", flagCode)
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immFlagCode = matcher.sub("imm8", flagCode)
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class RegOpChild(RegOp):
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mnemonic = name
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className = Name
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def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"):
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super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize)
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
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setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
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flagCode = regFlagCode, condCheck = condCode, elseCode = elseCode);
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class RegOpChildImm(RegOpImm):
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mnemonic = name + 'i'
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className = Name + 'Imm'
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def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"):
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super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize)
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microopClasses[name + 'i'] = RegOpChildImm
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setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
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setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
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flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode);
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
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defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)')
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defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
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defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
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defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True)
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defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
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defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True)
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defineMicroRegOp('Mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)')
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)',
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elseCode='DestReg=DestReg;', cc=True)
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# Shift instructions
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defineMicroRegOp('Sll', '''
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uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
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DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
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''')
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# There are special rules for the flag for a single bit shift
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defineMicroRegOp('Bll', '''
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DestReg = merge(DestReg, SrcReg1 << 1, dataSize);
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''')
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# This has it's own function because Wr ops have implicit destinations
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def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
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Name = mnemonic
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name = mnemonic.lower()
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# Find op2 in each of the instruction definitions. Create two versions
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = matcher.sub("SrcReg2", code)
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immCode = matcher.sub("imm8", code)
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class RegOpChild(RegOp):
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mnemonic = name
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className = Name
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def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
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super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
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setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
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condCheck = checkCCFlagBits, elseCode = elseCode);
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class RegOpChildImm(RegOpImm):
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mnemonic = name + 'i'
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className = Name + 'Imm'
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def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
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super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
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microopClasses[name + 'i'] = RegOpChildImm
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setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
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setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
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condCheck = checkCCFlagBits, elseCode = elseCode);
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defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;")
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# This has it's own function because Rd ops don't always have two parameters
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def defineMicroRegOpRd(mnemonic, code):
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Name = mnemonic
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name = mnemonic.lower()
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class RegOpChild(RegOp):
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def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
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super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
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self.className = Name
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self.mnemonic = name
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
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defineMicroRegOpRd('Rdip', 'DestReg = RIP')
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def defineMicroRegOpImm(mnemonic, code):
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Name = mnemonic
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name = mnemonic.lower()
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class RegOpChild(RegOpImm):
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def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
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super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
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self.className = Name
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self.mnemonic = name
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microopClasses[name] = RegOpChild
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setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
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defineMicroRegOpImm('Sext', '''
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IntReg val = SrcReg1;
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int sign_bit = bits(val, imm8-1, imm8-1);
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val = sign_bit ? (val | ~mask(imm8)) : val;
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DestReg = merge(DestReg, val, dataSize);''')
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defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);')
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}};
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