7359e2df01
arch/sparc/isa/bitfields.isa:
the trap field is 7:0
arch/sparc/isa/decoder.isa:
add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
We need the syscall num register
--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
50 lines
1.3 KiB
Text
50 lines
1.3 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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// Bitfields are shared liberally between instruction formats, so they are
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// simply defined alphabetically
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def bitfield A <29>;
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def bitfield CC02 <20>;
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def bitfield CC03 <25>;
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def bitfield CC04 <11>;
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def bitfield CC12 <21>;
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def bitfield CC13 <26>;
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def bitfield CC14 <12>;
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def bitfield CC2 <18>;
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def bitfield CMASK <6:4>;
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def bitfield COND2 <28:25>;
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def bitfield COND4 <17:14>;
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def bitfield D16HI <21:20>;
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def bitfield D16LO <13:0>;
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def bitfield DISP19 <18:0>;
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def bitfield DISP22 <21:0>;
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def bitfield DISP30 <29:0>;
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def bitfield FCN <29:26>;
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def bitfield I <13>;
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def bitfield IMM_ASI <12:5>;
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def bitfield IMM22 <21:0>;
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def bitfield MMASK <3:0>;
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def bitfield OP <31:30>;
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def bitfield OP2 <24:22>;
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def bitfield OP3 <24:19>;
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def bitfield OPF <13:5>;
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def bitfield OPF_CC <13:11>;
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def bitfield OPF_LOW5 <9:5>;
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def bitfield OPF_LOW6 <10:5>;
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def bitfield P <19>;
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def bitfield RCOND2 <27:25>;
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def bitfield RCOND3 <12:10>;
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def bitfield RCOND4 <12:10>;
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def bitfield RD <29:25>;
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def bitfield RS1 <18:14>;
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def bitfield RS2 <4:0>;
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def bitfield SHCNT32 <4:0>;
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def bitfield SHCNT64 <5:0>;
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def bitfield SIMM10 <9:0>;
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def bitfield SIMM11 <10:0>;
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def bitfield SIMM13 <12:0>;
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def bitfield SW_TRAP <7:0>;
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def bitfield X <12>;
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