2962 lines
347 KiB
Plaintext
2962 lines
347 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.824888 # Number of seconds simulated
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sim_ticks 2824887572500 # Number of ticks simulated
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final_tick 2824887572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 216723 # Simulator instruction rate (inst/s)
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host_op_rate 262904 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4977623525 # Simulator tick rate (ticks/s)
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host_mem_usage 565980 # Number of bytes of host memory used
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host_seconds 567.52 # Real time elapsed on the host
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sim_insts 122993828 # Number of instructions simulated
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sim_ops 149202488 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 541924 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4139684 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 101376 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 929664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 333376 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1678720 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.dtb.walker 4352 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 417152 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 3014592 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 11164040 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 541924 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 101376 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 333376 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 417152 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1393828 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 8400768 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8418292 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 16921 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 65202 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1584 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 14526 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 5209 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 26230 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.dtb.walker 68 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 6518 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 47103 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 183411 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 131262 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 135643 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 191839 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1465433 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 35887 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 329098 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 702 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 118014 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 594261 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.dtb.walker 1541 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 147670 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 1067155 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3952030 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 191839 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 35887 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 118014 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 147670 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 493410 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2973842 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6203 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2980045 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2973842 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 191839 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1471637 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 35887 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 329098 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 118014 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 594261 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.dtb.walker 1541 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 147670 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 1067155 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6932075 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 101269 # Number of read requests accepted
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system.physmem.writeReqs 69732 # Number of write requests accepted
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system.physmem.readBursts 101269 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 69732 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 6474944 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4461760 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 6481216 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4462848 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 6934 # Per bank write bursts
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system.physmem.perBankRdBursts::1 6434 # Per bank write bursts
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system.physmem.perBankRdBursts::2 6537 # Per bank write bursts
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system.physmem.perBankRdBursts::3 6251 # Per bank write bursts
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system.physmem.perBankRdBursts::4 6342 # Per bank write bursts
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system.physmem.perBankRdBursts::5 6194 # Per bank write bursts
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system.physmem.perBankRdBursts::6 6528 # Per bank write bursts
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system.physmem.perBankRdBursts::7 6694 # Per bank write bursts
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system.physmem.perBankRdBursts::8 6445 # Per bank write bursts
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system.physmem.perBankRdBursts::9 6959 # Per bank write bursts
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system.physmem.perBankRdBursts::10 6209 # Per bank write bursts
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system.physmem.perBankRdBursts::11 5533 # Per bank write bursts
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system.physmem.perBankRdBursts::12 5533 # Per bank write bursts
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system.physmem.perBankRdBursts::13 6776 # Per bank write bursts
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system.physmem.perBankRdBursts::14 6216 # Per bank write bursts
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system.physmem.perBankRdBursts::15 5586 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4691 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4256 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4619 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4200 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4373 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4446 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4606 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4292 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4489 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5118 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4307 # Per bank write bursts
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system.physmem.perBankWrBursts::11 3733 # Per bank write bursts
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system.physmem.perBankWrBursts::12 3760 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4801 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4212 # Per bank write bursts
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system.physmem.perBankWrBursts::15 3812 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
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system.physmem.totGap 2823321303500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 101269 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 69732 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 77442 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 21001 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2162 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 563 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 69 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1613 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3358 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 3597 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 3972 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 3735 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 3780 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 3876 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 3928 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4187 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4547 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4146 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4344 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4795 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4080 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 3977 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 3922 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 379 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 165 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 108 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 84 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 90 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 42 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 21 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 31 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 25 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 39430 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 277.365255 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 164.227213 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 309.241894 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 16179 41.03% 41.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 9599 24.34% 65.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 3886 9.86% 75.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2087 5.29% 80.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1608 4.08% 84.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1015 2.57% 87.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 638 1.62% 88.80% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 547 1.39% 90.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3871 9.82% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 39430 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 3587 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 28.196264 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 471.698929 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-1023 3585 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 3587 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 3587 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 19.435461 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.049607 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 11.402559 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 3 0.08% 0.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 3190 88.93% 89.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 86 2.40% 91.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 46 1.28% 92.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 29 0.81% 93.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 24 0.67% 94.40% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 7 0.20% 94.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 31 0.86% 95.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 8 0.22% 95.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 55 1.53% 97.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 9 0.25% 97.46% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 4 0.11% 97.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 7 0.20% 97.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 27 0.75% 98.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 2 0.06% 98.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 3 0.08% 98.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 13 0.36% 99.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 26 0.72% 99.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 1 0.03% 99.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 1 0.03% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 4 0.11% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.03% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 1 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 3587 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1320327750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 3217284000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 505855000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 13050.46 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31800.46 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 20.00 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 81754 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 49701 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 16510554.34 # Average gap between requests
|
|
system.physmem.pageHitRate 76.92 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 85131750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 404929200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 229929840 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 73278235845 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1622828751000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1876768379595 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 667.450508 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 2640406091750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 91914680000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 20314514250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 141802920 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 77215875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 384181200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 221823360 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 72833545215 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1617851985750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1871295668400 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 667.627988 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 2641096901750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 91914680000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 19627144250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.walks 4962 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksShort 4962 # Table walker walks initiated with short descriptors
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 4962 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0 4962 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 4962 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::mean 1.356186 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0 -18908123670 -35.62% -35.62% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::1 71993127250 135.62% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total 53085003580 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 2699 66.41% 66.41% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::1M 1365 33.59% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 4064 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4962 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4962 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4064 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4064 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 9026 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 11954908 # DTB read hits
|
|
system.cpu0.dtb.read_misses 4164 # DTB read misses
|
|
system.cpu0.dtb.write_hits 9290329 # DTB write hits
|
|
system.cpu0.dtb.write_misses 798 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 2862 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 165 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 11959072 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 9291127 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 21245237 # DTB hits
|
|
system.cpu0.dtb.misses 4962 # DTB misses
|
|
system.cpu0.dtb.accesses 21250199 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 2303 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksShort 2303 # Table walker walks initiated with short descriptors
|
|
system.cpu0.itb.walker.walkWaitTime::samples 2303 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 2303 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 2303 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::mean 1.356188 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 -18908264170 -35.62% -35.62% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::1 71993267750 135.62% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 53085003580 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 1258 73.83% 73.83% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::1M 446 26.17% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 1704 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2303 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2303 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1704 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1704 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 4007 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 57101564 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2303 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1710 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 57103867 # ITB inst accesses
|
|
system.cpu0.itb.hits 57101564 # DTB hits
|
|
system.cpu0.itb.misses 2303 # DTB misses
|
|
system.cpu0.itb.accesses 57103867 # DTB accesses
|
|
system.cpu0.numCycles 69056557 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 3089 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 55689685 # Number of instructions committed
|
|
system.cpu0.committedOps 67533645 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 59242517 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 4477 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 5745226 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 7381576 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 59242517 # number of integer instructions
|
|
system.cpu0.num_fp_insts 4477 # number of float instructions
|
|
system.cpu0.num_int_register_reads 109364432 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 41082844 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3371 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 205589269 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 25204829 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 21807623 # number of memory refs
|
|
system.cpu0.num_load_insts 12096876 # Number of load instructions
|
|
system.cpu0.num_store_insts 9710747 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 65266459.651417 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 3790097.348583 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.054884 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.945116 # Percentage of idle cycles
|
|
system.cpu0.Branches 13519232 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 46765026 68.14% 68.15% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 50017 0.07% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 3786 0.01% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.22% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 12096876 17.63% 85.85% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 9710747 14.15% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 68628631 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 834080 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.996936 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 46068701 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 834592 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 55.199069 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.869099 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 12.090258 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.459372 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.578207 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929432 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023614 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012616 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.034332 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 193256162 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 193256162 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 11356893 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 3664656 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 4328434 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu3.data 6496122 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 25846105 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 8947209 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 2625670 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 3368119 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu3.data 3982538 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18923536 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 168512 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54432 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75016 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87845 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 385805 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 206942 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74426 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 78729 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90116 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 450213 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 207891 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76401 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 81635 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 94165 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 460092 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 20304102 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 6290326 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 7696553 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu3.data 10478660 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 44769641 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 20472614 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 6344758 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 7771569 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu3.data 10566505 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 45155446 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 160217 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 56728 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 95563 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu3.data 209826 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 522334 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 126244 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 30952 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 98555 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu3.data 1104293 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1360044 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 49130 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 18052 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 32658 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 39211 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 139051 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3529 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2613 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3858 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8177 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 18177 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 29 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 286461 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 87680 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 194118 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu3.data 1314119 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1882378 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 335591 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 105732 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 226776 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu3.data 1353330 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2021429 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 1016014500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1426628000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3739680000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 6182322500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1887949500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6611273497 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 78305573428 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 86804796425 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 34719000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 55073500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 117380500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 207173000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 1140000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 1140000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 2903964000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 8037901497 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu3.data 82045253428 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 92987118925 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 2903964000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 8037901497 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu3.data 82045253428 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 92987118925 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11517110 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 3721384 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4423997 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu3.data 6705948 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 26368439 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9073453 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 2656622 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3466674 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu3.data 5086831 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 20283580 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 217642 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 72484 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 107674 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 127056 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 524856 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 210471 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77039 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 82587 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 98293 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 468390 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207891 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76401 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 81635 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 94194 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 460121 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 20590563 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 6378006 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 7890671 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu3.data 11792779 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 46652019 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 20808205 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 6450490 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 7998345 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu3.data 11919835 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 47176875 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013911 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015244 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021601 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031290 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.019809 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013914 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011651 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028429 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.217089 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.067051 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.225738 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249048 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.303304 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.308612 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264932 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016767 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033918 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.046714 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083190 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038807 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000308 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000063 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013912 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013747 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024601 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.111434 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.040349 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016128 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016391 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.028353 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.113536 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.042848 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17910.282400 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14928.664860 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17822.767436 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11835.956495 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60996.042259 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67082.070894 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70910.141989 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63824.991269 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13287.026406 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14275.142561 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14354.959031 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11397.535347 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 39310.344828 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 39310.344828 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 33120.027372 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41407.296062 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62433.655877 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 49398.749308 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27465.327432 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35444.233504 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60624.720820 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 46000.685122 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 503390 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 35294 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 12525 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 561 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.190818 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 62.912656 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 691847 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 691847 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 79 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15182 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 96539 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 111800 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 44856 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1015633 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1060489 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1591 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2377 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5420 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9388 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 79 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 60038 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu3.data 1112172 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1172289 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 79 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 60038 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu3.data 1112172 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1172289 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 56649 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 80381 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 113287 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 250317 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 30952 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53699 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 88660 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 173311 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 17774 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 22936 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 28713 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 69423 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1022 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1481 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2757 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5260 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 29 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 87601 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 134080 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu3.data 201947 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 423628 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 105375 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 157016 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu3.data 230660 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 493051 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3429 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5504 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8482 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17415 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2782 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4256 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6706 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13744 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6211 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 9760 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 15188 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31159 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 957693500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1167299000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1760783000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3885775500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1856997500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3570637000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6424728942 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11852363442 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 233240000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 318800500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 497243500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1049284000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 15367000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 25499000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 42983000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 83849000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 1111000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1111000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2814691000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4737936000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8185511942 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15738138942 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3047931000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 5056736500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8682755442 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 16787422942 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604453000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1092559500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1833275500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3530288000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 493653500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 837467000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1430846952 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2761967452 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1098106500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1930026500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3264122452 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6292255452 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015223 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018169 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016894 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009493 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011651 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015490 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017429 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008544 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245213 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.213013 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225987 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.132271 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013266 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028049 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.011230 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000308 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013735 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016992 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017125 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.009081 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016336 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019631 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019351 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.010451 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16905.744144 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14522.076113 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15542.674799 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15523.418306 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59996.042259 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66493.547366 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72464.797451 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68387.831367 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13122.538539 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13899.568364 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17317.713231 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15114.356913 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15036.203523 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17217.420662 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15590.496917 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15940.874525 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32130.809009 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35336.634845 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40532.971235 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37150.846833 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28924.612100 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32205.230677 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37643.091312 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34048.045622 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176276.757072 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198502.816134 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 216137.172837 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202715.360322 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177445.542775 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196773.261278 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213368.170593 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200958.050931 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176800.273708 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197748.616803 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214914.567553 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201940.224397 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1989175 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.436154 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 93885937 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1989687 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 47.186285 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 12780860000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 432.324798 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.897610 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.477932 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu3.inst 38.735813 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.844384 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021284 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.057574 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.075656 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.998899 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 227 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 97909665 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 97909665 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 56380254 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 17885752 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 10407436 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu3.inst 9212495 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 93885937 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 56380254 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 17885752 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 10407436 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu3.inst 9212495 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 93885937 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 56380254 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 17885752 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 10407436 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu3.inst 9212495 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 93885937 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 723014 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 206480 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 504682 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu3.inst 599818 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 2033994 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 723014 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 206480 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 504682 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu3.inst 599818 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 2033994 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 723014 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 206480 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 504682 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu3.inst 599818 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 2033994 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2883003500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 7207358000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 8637022483 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 18727383983 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 2883003500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 7207358000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu3.inst 8637022483 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 18727383983 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 2883003500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 7207358000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu3.inst 8637022483 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 18727383983 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57103268 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 18092232 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 10912118 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu3.inst 9812313 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 95919931 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 57103268 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 18092232 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 10912118 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu3.inst 9812313 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 95919931 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 57103268 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 18092232 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 10912118 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu3.inst 9812313 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 95919931 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012662 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011413 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.046250 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.061129 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.021205 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012662 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011413 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.046250 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.061129 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.021205 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012662 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011413 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.046250 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.061129 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.021205 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.628342 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14280.988821 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14399.405291 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 9207.197260 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13962.628342 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14280.988821 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14399.405291 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 9207.197260 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13962.628342 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14280.988821 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14399.405291 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 9207.197260 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 7487 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 343 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.827988 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 1989175 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 1989175 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 44259 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 44259 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu3.inst 44259 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 44259 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu3.inst 44259 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 44259 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 206480 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 504682 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 555559 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 1266721 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 206480 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 504682 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu3.inst 555559 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 1266721 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 206480 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 504682 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu3.inst 555559 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 1266721 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2676523500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6702677000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7539211985 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 16918412485 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2676523500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6702677000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7539211985 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 16918412485 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2676523500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6702677000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7539211985 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 16918412485 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011413 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.046250 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.056619 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013206 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011413 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.046250 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.056619 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.013206 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011413 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.046250 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.056619 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.013206 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12962.628342 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13280.990802 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13570.497436 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13356.068530 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12962.628342 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13280.990802 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13570.497436 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13356.068530 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12962.628342 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13280.990802 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13570.497436 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13356.068530 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 1864 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksShort 1864 # Table walker walks initiated with short descriptors
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 484 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1380 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 1864 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 1864 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 1864 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 1576 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 14376.903553 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 12683.026885 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 6626.503749 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::4096-6143 273 17.32% 17.32% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::6144-8191 48 3.05% 20.37% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::10240-12287 463 29.38% 49.75% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::12288-14335 60 3.81% 53.55% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::14336-16383 242 15.36% 68.91% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.44% 73.35% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::22528-24575 399 25.32% 98.67% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.33% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 1576 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 1094 69.42% 69.42% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::1M 482 30.58% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 1576 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1864 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1864 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1576 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1576 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 3440 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 3874336 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1644 # DTB read misses
|
|
system.cpu1.dtb.write_hits 2735867 # DTB write hits
|
|
system.cpu1.dtb.write_misses 220 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1077 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 240 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 62 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 3875980 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 2736087 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 6610203 # DTB hits
|
|
system.cpu1.dtb.misses 1864 # DTB misses
|
|
system.cpu1.dtb.accesses 6612067 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 917 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksShort 917 # Table walker walks initiated with short descriptors
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 740 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walkWaitTime::samples 917 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 917 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 917 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 666 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 13797.297297 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 12192.351828 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 6305.163791 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::4096-6143 141 21.17% 21.17% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.32% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.68% 47.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::12288-14335 40 6.01% 53.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::14336-16383 171 25.68% 78.68% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.57% 99.25% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.75% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 666 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 489 73.42% 73.42% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::1M 177 26.58% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 666 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 917 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 917 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 666 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 666 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 1583 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 18092232 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 917 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 697 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 18093149 # ITB inst accesses
|
|
system.cpu1.itb.hits 18092232 # DTB hits
|
|
system.cpu1.itb.misses 917 # DTB misses
|
|
system.cpu1.itb.accesses 18093149 # DTB accesses
|
|
system.cpu1.numCycles 144011117 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 17422083 # Number of instructions committed
|
|
system.cpu1.committedOps 20907241 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 18575942 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1372 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 1991871 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 2240039 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 18575942 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1372 # number of float instructions
|
|
system.cpu1.num_int_register_reads 34372457 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 13029259 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1112 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 76102433 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 7596638 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 6802434 # number of memory refs
|
|
system.cpu1.num_load_insts 3915999 # Number of load instructions
|
|
system.cpu1.num_store_insts 2886435 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 136776220.801950 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 7234896.198050 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.050238 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.949762 # Percentage of idle cycles
|
|
system.cpu1.Branches 4344241 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 21 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 14689053 68.29% 68.29% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 16409 0.08% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 960 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.37% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 3915999 18.21% 86.58% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 2886435 13.42% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 21508877 # Class of executed instruction
|
|
system.cpu2.branchPred.lookups 5793612 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 2980826 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 510173 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 3341090 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 2404622 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 71.971183 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 1623448 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 331512 # Number of incorrect RAS predictions.
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.dtb.walker.walks 13179 # Table walker walks requested
|
|
system.cpu2.dtb.walker.walksShort 13179 # Table walker walks initiated with short descriptors
|
|
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8247 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4932 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu2.dtb.walker.walkWaitTime::samples 13179 # Table walker wait (enqueue to first request) latency
|
|
system.cpu2.dtb.walker.walkWaitTime::0 13179 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu2.dtb.walker.walkWaitTime::total 13179 # Table walker wait (enqueue to first request) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::samples 2214 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::mean 13311.653117 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::gmean 11619.348750 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.573667 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::0-32767 2213 99.95% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::262144-294911 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walkCompletionTime::total 2214 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution
|
|
system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution
|
|
system.cpu2.dtb.walker.walkPageSizes::4K 1376 62.15% 62.15% # Table walker page sizes translated
|
|
system.cpu2.dtb.walker.walkPageSizes::1M 838 37.85% 100.00% # Table walker page sizes translated
|
|
system.cpu2.dtb.walker.walkPageSizes::total 2214 # Table walker page sizes translated
|
|
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13179 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13179 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2214 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2214 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.walker.walkRequestOrigin::total 15393 # Table walker requests started/completed, data/inst
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 4658745 # DTB read hits
|
|
system.cpu2.dtb.read_misses 11783 # DTB read misses
|
|
system.cpu2.dtb.write_hits 3577519 # DTB write hits
|
|
system.cpu2.dtb.write_misses 1396 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 1514 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 206 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 331 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 4670528 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 3578915 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 8236264 # DTB hits
|
|
system.cpu2.dtb.misses 13179 # DTB misses
|
|
system.cpu2.dtb.accesses 8249443 # DTB accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.itb.walker.walks 1381 # Table walker walks requested
|
|
system.cpu2.itb.walker.walksShort 1381 # Table walker walks initiated with short descriptors
|
|
system.cpu2.itb.walker.walksShortTerminationLevel::Level1 251 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1130 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu2.itb.walker.walkWaitTime::samples 1381 # Table walker wait (enqueue to first request) latency
|
|
system.cpu2.itb.walker.walkWaitTime::0 1381 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu2.itb.walker.walkWaitTime::total 1381 # Table walker wait (enqueue to first request) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::samples 875 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::mean 13237.714286 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::gmean 11667.376673 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::stdev 6208.114147 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::4096-6143 218 24.91% 24.91% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 25.03% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 27.54% 52.57% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::12288-14335 34 3.89% 56.46% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 24.69% 81.14% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::22528-24575 162 18.51% 99.66% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.34% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walkCompletionTime::total 875 # Table walker service (enqueue to completion) latency
|
|
system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution
|
|
system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution
|
|
system.cpu2.itb.walker.walkPageSizes::4K 624 71.31% 71.31% # Table walker page sizes translated
|
|
system.cpu2.itb.walker.walkPageSizes::1M 251 28.69% 100.00% # Table walker page sizes translated
|
|
system.cpu2.itb.walker.walkPageSizes::total 875 # Table walker page sizes translated
|
|
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1381 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1381 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 875 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 875 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.walker.walkRequestOrigin::total 2256 # Table walker requests started/completed, data/inst
|
|
system.cpu2.itb.inst_hits 10914034 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 1381 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1797 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 10915415 # ITB inst accesses
|
|
system.cpu2.itb.hits 10914034 # DTB hits
|
|
system.cpu2.itb.misses 1381 # DTB misses
|
|
system.cpu2.itb.accesses 10915415 # DTB accesses
|
|
system.cpu2.numCycles 1393570543 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 20500176 # Number of instructions committed
|
|
system.cpu2.committedOps 24831062 # Number of ops (including micro ops) committed
|
|
system.cpu2.discardedOps 1467933 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu2.numFetchSuspends 564 # Number of times Execute suspended instruction fetching
|
|
system.cpu2.quiesceCycles 4256215364 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.cpi 67.978467 # CPI: cycles per instruction
|
|
system.cpu2.ipc 0.014711 # IPC: instructions per cycle
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.tickCycles 42639934 # Number of cycles that the object actually ticked
|
|
system.cpu2.idleCycles 1350930609 # Total number of cycles that the object has spent stopped
|
|
system.cpu3.branchPred.lookups 13289019 # Number of BP lookups
|
|
system.cpu3.branchPred.condPredicted 7253126 # Number of conditional branches predicted
|
|
system.cpu3.branchPred.condIncorrect 312439 # Number of conditional branches incorrect
|
|
system.cpu3.branchPred.BTBLookups 8263558 # Number of BTB lookups
|
|
system.cpu3.branchPred.BTBHits 6253160 # Number of BTB hits
|
|
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.branchPred.BTBHitPct 75.671521 # BTB Hit Percentage
|
|
system.cpu3.branchPred.usedRAS 3098416 # Number of times the RAS was used to get a target.
|
|
system.cpu3.branchPred.RASInCorrect 16246 # Number of incorrect RAS predictions.
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu3.dtb.walker.walks 32928 # Table walker walks requested
|
|
system.cpu3.dtb.walker.walksShort 32928 # Table walker walks initiated with short descriptors
|
|
system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11539 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7550 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu3.dtb.walker.walksSquashedBefore 13839 # Table walks squashed before starting
|
|
system.cpu3.dtb.walker.walkWaitTime::samples 19089 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::mean 453.769186 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::stdev 3060.650979 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::0-8191 18684 97.88% 97.88% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::8192-16383 255 1.34% 99.21% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.70% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::24576-32767 26 0.14% 99.83% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::32768-40959 12 0.06% 99.90% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::40960-49151 11 0.06% 99.95% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.98% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::65536-73727 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkWaitTime::total 19089 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::samples 6197 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::mean 13294.578022 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::gmean 10885.248950 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::stdev 8635.189295 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::0-16383 4539 73.25% 73.25% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1528 24.66% 97.90% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::32768-49151 104 1.68% 99.58% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::49152-65535 10 0.16% 99.74% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::65536-81919 13 0.21% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walkCompletionTime::total 6197 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.dtb.walker.walksPending::samples -8048051564 # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::mean 0.976034 # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::0-1 -8093653564 100.57% 100.57% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::2-3 33199000 -0.41% 100.15% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::4-5 6574500 -0.08% 100.07% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::6-7 2215500 -0.03% 100.04% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::8-9 1246000 -0.02% 100.03% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::10-11 692500 -0.01% 100.02% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::12-13 364000 -0.00% 100.02% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::14-15 852000 -0.01% 100.01% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::16-17 153000 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::18-19 182500 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::20-21 65500 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::24-25 20000 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walksPending::total -8048051564 # Table walker pending requests distribution
|
|
system.cpu3.dtb.walker.walkPageSizes::4K 1804 69.07% 69.07% # Table walker page sizes translated
|
|
system.cpu3.dtb.walker.walkPageSizes::1M 808 30.93% 100.00% # Table walker page sizes translated
|
|
system.cpu3.dtb.walker.walkPageSizes::total 2612 # Table walker page sizes translated
|
|
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32928 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32928 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2612 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2612 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.walker.walkRequestOrigin::total 35540 # Table walker requests started/completed, data/inst
|
|
system.cpu3.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu3.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu3.dtb.read_hits 7260437 # DTB read hits
|
|
system.cpu3.dtb.read_misses 28509 # DTB read misses
|
|
system.cpu3.dtb.write_hits 5425830 # DTB write hits
|
|
system.cpu3.dtb.write_misses 4419 # DTB write misses
|
|
system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed
|
|
system.cpu3.dtb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA
|
|
system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu3.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB
|
|
system.cpu3.dtb.align_faults 485 # Number of TLB faults due to alignment restrictions
|
|
system.cpu3.dtb.prefetch_faults 810 # Number of TLB faults due to prefetch
|
|
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu3.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions
|
|
system.cpu3.dtb.read_accesses 7288946 # DTB read accesses
|
|
system.cpu3.dtb.write_accesses 5430249 # DTB write accesses
|
|
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu3.dtb.hits 12686267 # DTB hits
|
|
system.cpu3.dtb.misses 32928 # DTB misses
|
|
system.cpu3.dtb.accesses 12719195 # DTB accesses
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu3.itb.walker.walks 4959 # Table walker walks requested
|
|
system.cpu3.itb.walker.walksShort 4959 # Table walker walks initiated with short descriptors
|
|
system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1575 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2956 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu3.itb.walker.walksSquashedBefore 428 # Table walks squashed before starting
|
|
system.cpu3.itb.walker.walkWaitTime::samples 4531 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::mean 1378.172589 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::stdev 5474.247381 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::0-8191 4267 94.17% 94.17% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::8192-16383 125 2.76% 96.93% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::16384-24575 86 1.90% 98.83% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.54% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.20% 99.74% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.82% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.89% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.93% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkWaitTime::total 4531 # Table walker wait (enqueue to first request) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::samples 1743 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::mean 12810.097533 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::gmean 10341.257314 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::stdev 8222.199176 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.38% 1.38% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::4096-8191 622 35.69% 37.06% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::8192-12287 348 19.97% 57.03% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::12288-16383 324 18.59% 75.62% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::16384-20479 26 1.49% 77.11% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::20480-24575 315 18.07% 95.18% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::24576-28671 50 2.87% 98.05% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.34% 98.39% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::32768-36863 6 0.34% 98.74% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::36864-40959 6 0.34% 99.08% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.46% 99.54% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.23% 99.77% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.06% 99.83% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.11% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walkCompletionTime::total 1743 # Table walker service (enqueue to completion) latency
|
|
system.cpu3.itb.walker.walksPending::samples -4005171768 # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::mean -0.325586 # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::0 -5306419980 132.49% 132.49% # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::1 1298923212 -32.43% 100.06% # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::2 1978000 -0.05% 100.01% # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::3 238000 -0.01% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::4 109000 -0.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walksPending::total -4005171768 # Table walker pending requests distribution
|
|
system.cpu3.itb.walker.walkPageSizes::4K 967 73.54% 73.54% # Table walker page sizes translated
|
|
system.cpu3.itb.walker.walkPageSizes::1M 348 26.46% 100.00% # Table walker page sizes translated
|
|
system.cpu3.itb.walker.walkPageSizes::total 1315 # Table walker page sizes translated
|
|
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4959 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4959 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1315 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1315 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.walker.walkRequestOrigin::total 6274 # Table walker requests started/completed, data/inst
|
|
system.cpu3.itb.inst_hits 9813721 # ITB inst hits
|
|
system.cpu3.itb.inst_misses 4959 # ITB inst misses
|
|
system.cpu3.itb.read_hits 0 # DTB read hits
|
|
system.cpu3.itb.read_misses 0 # DTB read misses
|
|
system.cpu3.itb.write_hits 0 # DTB write hits
|
|
system.cpu3.itb.write_misses 0 # DTB write misses
|
|
system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed
|
|
system.cpu3.itb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA
|
|
system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu3.itb.flush_entries 1311 # Number of entries that have been flushed from TLB
|
|
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu3.itb.perms_faults 728 # Number of TLB faults due to permissions restrictions
|
|
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu3.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu3.itb.inst_accesses 9818680 # ITB inst accesses
|
|
system.cpu3.itb.hits 9813721 # DTB hits
|
|
system.cpu3.itb.misses 4959 # DTB misses
|
|
system.cpu3.itb.accesses 9818680 # DTB accesses
|
|
system.cpu3.numCycles 58198977 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.fetch.icacheStallCycles 20997510 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.Insts 52319874 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.Branches 13289019 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.predictedBranches 9351576 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.Cycles 34146869 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.SquashCycles 1603241 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.TlbCycles 75601 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu3.fetch.MiscStallCycles 830 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu3.fetch.PendingDrainCycles 252 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu3.fetch.PendingTrapStallCycles 167692 # Number of stall cycles due to pending traps
|
|
system.cpu3.fetch.PendingQuiesceStallCycles 75270 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu3.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR
|
|
system.cpu3.fetch.CacheLines 9812317 # Number of cache lines fetched
|
|
system.cpu3.fetch.IcacheSquashes 215159 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.ItlbSquashes 2588 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu3.fetch.rateDist::samples 56266104 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.124866 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.272811 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 42091874 74.81% 74.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 1838725 3.27% 78.08% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 1172268 2.08% 80.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 3680170 6.54% 86.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 919176 1.63% 88.33% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 559542 0.99% 89.33% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 2920436 5.19% 94.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 600253 1.07% 95.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 2483660 4.41% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 56266104 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.branchRate 0.228338 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.rate 0.898983 # Number of inst fetches per cycle
|
|
system.cpu3.decode.IdleCycles 14691998 # Number of cycles decode is idle
|
|
system.cpu3.decode.BlockedCycles 32127735 # Number of cycles decode is blocked
|
|
system.cpu3.decode.RunCycles 7847757 # Number of cycles decode is running
|
|
system.cpu3.decode.UnblockCycles 886811 # Number of cycles decode is unblocking
|
|
system.cpu3.decode.SquashCycles 711602 # Number of cycles decode is squashing
|
|
system.cpu3.decode.BranchResolved 982939 # Number of times decode resolved a branch
|
|
system.cpu3.decode.BranchMispred 91189 # Number of times decode detected a branch misprediction
|
|
system.cpu3.decode.DecodedInsts 45025985 # Number of instructions handled by decode
|
|
system.cpu3.decode.SquashedInsts 297573 # Number of squashed instructions handled by decode
|
|
system.cpu3.rename.SquashCycles 711602 # Number of cycles rename is squashing
|
|
system.cpu3.rename.IdleCycles 15176381 # Number of cycles rename is idle
|
|
system.cpu3.rename.BlockCycles 3842485 # Number of cycles rename is blocking
|
|
system.cpu3.rename.serializeStallCycles 22070368 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RunCycles 8242497 # Number of cycles rename is running
|
|
system.cpu3.rename.UnblockCycles 6222544 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RenamedInsts 43140081 # Number of instructions processed by rename
|
|
system.cpu3.rename.ROBFullEvents 802 # Number of times rename has blocked due to ROB full
|
|
system.cpu3.rename.IQFullEvents 912982 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.LQFullEvents 87651 # Number of times rename has blocked due to LQ full
|
|
system.cpu3.rename.SQFullEvents 4846837 # Number of times rename has blocked due to SQ full
|
|
system.cpu3.rename.RenamedOperands 44765157 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RenameLookups 198174110 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.int_rename_lookups 48152546 # Number of integer rename lookups
|
|
system.cpu3.rename.fp_rename_lookups 3891 # Number of floating rename lookups
|
|
system.cpu3.rename.CommittedMaps 37263168 # Number of HB maps that are committed
|
|
system.cpu3.rename.UndoneMaps 7501989 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.serializingInsts 722657 # count of serializing insts renamed
|
|
system.cpu3.rename.tempSerializingInsts 671168 # count of temporary serializing insts renamed
|
|
system.cpu3.rename.skidInsts 5019030 # count of insts added to the skid buffer
|
|
system.cpu3.memDep0.insertedLoads 7753962 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 6001781 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.conflictingLoads 1096461 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 1526920 # Number of conflicting stores.
|
|
system.cpu3.iq.iqInstsAdded 41470903 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqNonSpecInstsAdded 516515 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqInstsIssued 39452509 # Number of instructions issued
|
|
system.cpu3.iq.iqSquashedInstsIssued 52405 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedInstsExamined 6056878 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedOperandsExamined 13877375 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 54814 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.issued_per_cycle::samples 56266104 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::mean 0.701177 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.409085 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::0 40628428 72.21% 72.21% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::1 5180351 9.21% 81.41% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::2 3993172 7.10% 88.51% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::3 3216769 5.72% 94.23% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::4 1270144 2.26% 96.49% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::5 778707 1.38% 97.87% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::6 841867 1.50% 99.37% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::7 243134 0.43% 99.80% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::8 113532 0.20% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::total 56266104 # Number of insts issued each cycle
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntAlu 56907 9.43% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemRead 285269 47.26% 56.69% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemWrite 261388 43.31% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.FU_type_0::No_OpClass 82 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntAlu 26244378 66.52% 66.52% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntMult 29732 0.08% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 2423 0.01% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.60% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemRead 7478738 18.96% 85.56% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemWrite 5697150 14.44% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::total 39452509 # Type of FU issued
|
|
system.cpu3.iq.rate 0.677890 # Inst issue rate
|
|
system.cpu3.iq.fu_busy_cnt 603564 # FU busy when requested
|
|
system.cpu3.iq.fu_busy_rate 0.015298 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.int_inst_queue_reads 135818664 # Number of integer instruction queue reads
|
|
system.cpu3.iq.int_inst_queue_writes 48068982 # Number of integer instruction queue writes
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 38286246 # Number of integer instruction queue wakeup accesses
|
|
system.cpu3.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads
|
|
system.cpu3.iq.fp_inst_queue_writes 4554 # Number of floating instruction queue writes
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 3686 # Number of floating instruction queue wakeup accesses
|
|
system.cpu3.iq.int_alu_accesses 40051464 # Number of integer alu accesses
|
|
system.cpu3.iq.fp_alu_accesses 4527 # Number of floating point alu accesses
|
|
system.cpu3.iew.lsq.thread0.forwLoads 171911 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 1183804 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 1366 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 29886 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread0.squashedStores 609084 # Number of stores squashed
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 109633 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 44383 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewSquashCycles 711602 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewBlockCycles 3194648 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewUnblockCycles 528279 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.iewDispatchedInsts 42035264 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewDispSquashedInsts 85063 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispLoadInsts 7753962 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispStoreInsts 6001781 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 267022 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewIQFullEvents 22471 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewLSQFullEvents 499621 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.memOrderViolationEvents 29886 # Number of memory order violations
|
|
system.cpu3.iew.predictedTakenIncorrect 141382 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.iew.predictedNotTakenIncorrect 125809 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.branchMispredicts 267191 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewExecutedInsts 39120156 # Number of executed instructions
|
|
system.cpu3.iew.iewExecLoadInsts 7345638 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 299518 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu3.iew.exec_nop 47846 # number of nop insts executed
|
|
system.cpu3.iew.exec_refs 12983277 # number of memory reference insts executed
|
|
system.cpu3.iew.exec_branches 7265357 # Number of branches executed
|
|
system.cpu3.iew.exec_stores 5637639 # Number of stores executed
|
|
system.cpu3.iew.exec_rate 0.672179 # Inst execution rate
|
|
system.cpu3.iew.wb_sent 38830479 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.wb_count 38289932 # cumulative count of insts written-back
|
|
system.cpu3.iew.wb_producers 20020734 # num instructions producing a value
|
|
system.cpu3.iew.wb_consumers 34859038 # num instructions consuming a value
|
|
system.cpu3.iew.wb_rate 0.657914 # insts written-back per cycle
|
|
system.cpu3.iew.wb_fanout 0.574334 # average fanout of values written-back
|
|
system.cpu3.commit.commitSquashedInsts 6072535 # The number of squashed insts skipped by commit
|
|
system.cpu3.commit.commitNonSpecStalls 461701 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.branchMispredicts 222399 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.committed_per_cycle::samples 54967240 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::mean 0.654139 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::stdev 1.550137 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::0 41117767 74.80% 74.80% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::1 6171974 11.23% 86.03% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::2 3094219 5.63% 91.66% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::3 1318133 2.40% 94.06% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::4 709863 1.29% 95.35% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::5 496595 0.90% 96.25% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::6 959944 1.75% 98.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::7 230664 0.42% 98.42% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::8 868081 1.58% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::total 54967240 # Number of insts commited each cycle
|
|
system.cpu3.commit.committedInsts 29407542 # Number of instructions committed
|
|
system.cpu3.commit.committedOps 35956198 # Number of ops (including micro ops) committed
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.refs 11962855 # Number of memory references committed
|
|
system.cpu3.commit.loads 6570158 # Number of loads committed
|
|
system.cpu3.commit.membars 179658 # Number of memory barriers committed
|
|
system.cpu3.commit.branches 6851927 # Number of branches committed
|
|
system.cpu3.commit.fp_insts 3664 # Number of committed floating point instructions.
|
|
system.cpu3.commit.int_insts 31411124 # Number of committed integer instructions.
|
|
system.cpu3.commit.function_calls 1242322 # Number of function calls committed.
|
|
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntAlu 23962177 66.64% 66.64% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntMult 28743 0.08% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.72% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMisc 2423 0.01% 66.73% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.73% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.73% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.73% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemRead 6570158 18.27% 85.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemWrite 5392697 15.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::total 35956198 # Class of committed instruction
|
|
system.cpu3.commit.bw_lim_events 868081 # number cycles where commit BW limit reached
|
|
system.cpu3.rob.rob_reads 90502636 # The number of ROB reads
|
|
system.cpu3.rob.rob_writes 85356048 # The number of ROB writes
|
|
system.cpu3.timesIdled 229941 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.idleCycles 1932873 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.quiesceCycles 5160445886 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu3.committedInsts 29381884 # Number of Instructions Simulated
|
|
system.cpu3.committedOps 35930540 # Number of Ops (including micro ops) Simulated
|
|
system.cpu3.cpi 1.980778 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 1.980778 # CPI: Total CPI of All Threads
|
|
system.cpu3.ipc 0.504852 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 0.504852 # IPC: Total IPC of All Threads
|
|
system.cpu3.int_regfile_reads 42608417 # number of integer regfile reads
|
|
system.cpu3.int_regfile_writes 24235283 # number of integer regfile writes
|
|
system.cpu3.fp_regfile_reads 14369 # number of floating regfile reads
|
|
system.cpu3.fp_regfile_writes 12266 # number of floating regfile writes
|
|
system.cpu3.cc_regfile_reads 138322316 # number of cc regfile reads
|
|
system.cpu3.cc_regfile_writes 14832721 # number of cc regfile writes
|
|
system.cpu3.misc_regfile_reads 76348373 # number of misc regfile reads
|
|
system.cpu3.misc_regfile_writes 345208 # number of misc regfile writes
|
|
system.iobus.trans_dist::ReadReq 30184 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30184 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59010 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178388 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480341 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 27681500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 206500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 12500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 3853000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 22107500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 78671523 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 47950000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 15518000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.005787 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 249220700509 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.005787 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.062862 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.062862 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328284 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 18163419 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 18163419 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 1912585104 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 1912585104 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 18163419 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 18163419 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 18163419 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 18163419 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 72077.059524 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 72077.059524 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52798.837898 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 52798.837898 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 72077.059524 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 72077.059524 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 151 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 15216 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 15216 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 151 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 151 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 151 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 10613419 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 10613419 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1151112953 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 1151112953 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 10613419 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 10613419 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 10613419 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 10613419 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.599206 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.420053 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 0.420053 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.599206 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.599206 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70287.543046 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 70287.543046 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75651.482190 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75651.482190 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 104075 # number of replacements
|
|
system.l2c.tags.tagsinuse 65088.742939 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 5172869 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 169255 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 30.562577 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 80144379500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 48905.220399 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971842 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4329.133912 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2210.348927 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 681.885692 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 812.281679 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.dtb.walker 23.888287 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 2283.545519 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 778.271675 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.750062 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 3339.743961 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 1673.700888 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.746234 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.066057 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.033727 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.010405 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.012394 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000365 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.034844 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.011875 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000759 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.050960 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.025539 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.993175 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65123 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 7577 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 55266 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000870 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.993698 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 45714776 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 45714776 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 4211 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 2125 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 1917 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 966 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 14552 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 1305 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.dtb.walker 20572 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.itb.walker 4671 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 50319 # number of ReadReq hits
|
|
system.l2c.WritebackDirty_hits::writebacks 691847 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 691847 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 1951174 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 1951174 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu3.data 40 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 62 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu3.data 18 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 18 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 65749 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 18265 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 28449 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu3.data 44469 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 156932 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 715102 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 204893 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 499456 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu3.inst 548923 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1968374 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 206806 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 72955 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 102781 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3.data 140486 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 523028 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 4211 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 2125 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 715102 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 272555 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 1917 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 966 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 204893 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 91220 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 14552 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 1305 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 499456 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 131230 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.dtb.walker 20572 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.itb.walker 4671 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 548923 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 184955 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2698653 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 4211 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 2125 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 715102 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 272555 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 1917 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 966 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 204893 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 91220 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 14552 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 1305 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 499456 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 131230 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.dtb.walker 20572 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.itb.walker 4671 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 548923 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 184955 # number of overall hits
|
|
system.l2c.overall_hits::total 2698653 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.dtb.walker 68 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 103 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1107 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 355 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 584 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 705 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2751 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu3.data 11 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 11 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 59379 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 12331 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 24655 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 43452 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 139817 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 7904 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 1584 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 5216 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu3.inst 6524 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 21228 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 6070 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 2490 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 2016 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3.data 4265 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 14841 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7904 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 65449 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1584 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 14821 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 5216 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 26671 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.dtb.walker 68 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 6524 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 47717 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 175989 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7904 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 65449 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1584 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 14821 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 5216 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 26671 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.dtb.walker 68 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 6524 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 47717 # number of overall misses
|
|
system.l2c.overall_misses::total 175989 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 4151500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 9155500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 13307000 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 157000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 233500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu3.data 937000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 1327500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 395000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 395000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1590644000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 3143584000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 5761072000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 10495300000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 207955000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 689811500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 871388999 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 1769155499 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 324931000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 266547000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3.data 582043000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 1173521000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 207955000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1915575000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 4151500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 689811500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 3410131000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.dtb.walker 9155500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 871388999 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 6343115000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 13451283499 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 207955000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1915575000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 4151500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 689811500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 3410131000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.dtb.walker 9155500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 871388999 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 6343115000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 13451283499 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4214 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 2126 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 1917 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 966 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.dtb.walker 14583 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.itb.walker 1305 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.dtb.walker 20640 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.itb.walker 4671 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 50422 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::writebacks 691847 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 691847 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 1951174 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 1951174 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1116 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 356 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 596 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 745 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2813 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu3.data 29 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 29 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 125128 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 30596 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 53104 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 87921 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 296749 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 723006 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 206477 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 504672 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu3.inst 555447 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1989602 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 212876 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 75445 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 104797 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3.data 144751 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 537869 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 4214 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 2126 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 723006 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 338004 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 1917 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 966 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 206477 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 106041 # number of demand (read+write) accesses
|
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system.l2c.demand_accesses::cpu2.dtb.walker 14583 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.itb.walker 1305 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 504672 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 157901 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.dtb.walker 20640 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.itb.walker 4671 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 555447 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 232672 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2874642 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 4214 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 2126 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 723006 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 338004 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 1917 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 966 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 206477 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 106041 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.dtb.walker 14583 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.itb.walker 1305 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 504672 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 157901 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.dtb.walker 20640 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.itb.walker 4671 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 555447 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 232672 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2874642 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000712 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000470 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002126 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003295 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.002043 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991935 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.997191 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.979866 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 0.946309 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.977959 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.379310 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.379310 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.474546 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.403027 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.464278 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 0.494216 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.471162 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010932 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007672 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.010335 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.011745 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.010669 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.028514 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.033004 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.019237 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.029464 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.027592 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000712 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000470 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.010932 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.193634 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.007672 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.139767 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002126 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.010335 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.168910 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003295 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.011745 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.205083 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.061221 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000712 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000470 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.010932 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.193634 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.007672 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.139767 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002126 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.010335 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.168910 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003295 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.011745 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.205083 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.061221 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 133919.354839 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 134639.705882 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 129194.174757 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 442.253521 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 399.828767 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 1329.078014 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 482.551799 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 35909.090909 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 35909.090909 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128995.539697 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127502.900020 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132584.737181 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 75064.548660 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131284.722222 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132249.137270 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 133566.676732 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 83340.658517 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130494.377510 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 132215.773810 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 136469.636577 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 79072.906138 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 131284.722222 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 129247.351731 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 133919.354839 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 132249.137270 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 127859.135390 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 134639.705882 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 133566.676732 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 132931.973930 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 76432.524186 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 131284.722222 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 129247.351731 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 133919.354839 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 132249.137270 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 127859.135390 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 134639.705882 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 133566.676732 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 132931.973930 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 76432.524186 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 95072 # number of writebacks
|
|
system.l2c.writebacks::total 95072 # number of writebacks
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 3 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 20 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 43 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 63 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 20 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 6 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.data 43 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 20 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 6 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.data 43 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 31 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 68 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 355 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 584 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 705 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 1644 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 11 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 11 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 12331 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 24655 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 43452 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 80438 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1584 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5213 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 6518 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 13315 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2490 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1996 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4222 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 8708 # number of ReadSharedReq MSHR misses
|
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|
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|
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|
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|
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system.l2c.demand_mshr_misses::cpu3.dtb.walker 68 # number of demand (read+write) MSHR misses
|
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system.l2c.demand_mshr_misses::cpu3.inst 6518 # number of demand (read+write) MSHR misses
|
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system.l2c.demand_mshr_misses::cpu3.data 47674 # number of demand (read+write) MSHR misses
|
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system.l2c.demand_mshr_misses::total 102560 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses::cpu1.inst 1584 # number of overall MSHR misses
|
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system.l2c.overall_mshr_misses::cpu1.data 14821 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu3.dtb.walker 68 # number of overall MSHR misses
|
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system.l2c.overall_mshr_misses::cpu3.inst 6518 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu3.data 47674 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 102560 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3429 # number of ReadReq MSHR uncacheable
|
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|
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system.l2c.ReadReq_mshr_uncacheable::cpu3.data 8482 # number of ReadReq MSHR uncacheable
|
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system.l2c.ReadReq_mshr_uncacheable::total 17415 # number of ReadReq MSHR uncacheable
|
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system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2782 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4256 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6706 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 13744 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6211 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 9760 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu3.data 15188 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 31159 # number of overall MSHR uncacheable misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3841500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 8475500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 12317000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24147500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 39692000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 47957000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 111796500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 754000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 754000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1467334000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2897034000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5326551501 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 9690919501 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 192115000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 637521000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 805608003 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 1635244003 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 300031000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 244243501 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 534307002 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 1078581503 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 192115000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1767365000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3841500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 637521000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 3141277501 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 8475500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 805608003 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 5860858503 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 12417062007 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 192115000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1767365000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3841500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 637521000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 3141277501 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 8475500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 805608003 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 5860858503 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 12417062007 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 561571500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1023750500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1727240000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 3312562000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 461641500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 788519000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1353656000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 2603816500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1023213000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1812269500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 3080896000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 5916378500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002126 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003295 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.001963 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.997191 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.979866 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.946309 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.584429 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.379310 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.379310 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.403027 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.464278 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.494216 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.271064 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007672 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010329 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011735 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006692 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033004 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019046 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.029167 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016190 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007672 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.139767 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002126 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010329 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.168783 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003295 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011735 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.204898 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.035677 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007672 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.139767 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002126 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010329 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.168783 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003295 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011735 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.204898 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.035677 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 124414.141414 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68021.126761 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 67965.753425 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68024.113475 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68002.737226 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68545.454545 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68545.454545 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118995.539697 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117502.900020 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122584.725697 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120476.882829 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121284.722222 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122294.456167 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123597.422983 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122812.166955 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120494.377510 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122366.483467 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 126553.055898 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 123860.990239 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121284.722222 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119247.351731 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122294.456167 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117867.153240 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123597.422983 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122936.160234 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 121071.197416 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121284.722222 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119247.351731 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122294.456167 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117867.153240 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123597.422983 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122936.160234 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 121071.197416 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163771.216098 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186001.180959 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.934921 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190213.149584 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165938.713156 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185272.321429 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201857.441098 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189451.142317 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164742.070520 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185683.350410 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.671583 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.033923 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 76465 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27565 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 131262 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 9255 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4560 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 1783 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 138008 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 138008 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 36351 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486392 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 593844 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94027 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 94027 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 687871 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273404 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 17436529 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2322624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2322624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 19759153 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 308 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 423355 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 423355 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 423355 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 54051500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 682000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 487313006 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 582602000 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 785081 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.snoop_filter.tot_requests 5677345 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2853013 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 45306 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 358 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 358 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 112463 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2640157 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 761584 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 1989175 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 147491 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2813 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2842 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 296749 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 296749 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1989735 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 538020 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 15216 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5986563 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626405 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26917 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102214 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 8742099 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254678264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97882489 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44408 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182720 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 352787881 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 192824 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 4204353 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.021421 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.144784 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 4114290 97.86% 97.86% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 90063 2.14% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 4204353 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 3491124499 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 176919 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1900767119 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 770214712 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 11666477 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 48138206 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|