0acd2a96e5
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions.
257 lines
7.2 KiB
C++
257 lines
7.2 KiB
C++
/* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Timothy M. Jones
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*/
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#ifndef __ARCH_POWER_INSTS_BRANCH_HH__
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#define __ARCH_POWER_INSTS_BRANCH_HH__
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#include "arch/power/insts/static_inst.hh"
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namespace PowerISA
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{
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/**
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* Base class for instructions whose disassembly is not purely a
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* function of the machine instruction (i.e., it depends on the
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* PC). This class overrides the disassemble() method to check
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* the PC and symbol table values before re-using a cached
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* disassembly string. This is necessary for branches and jumps,
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public PowerStaticInst
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: PowerStaticInst(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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}
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const std::string &
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disassemble(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for unconditional, PC-relative branches.
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*/
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class BranchPCRel : public PCDependentDisassembly
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{
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protected:
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/// Displacement
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uint32_t disp;
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/// Constructor.
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BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(machInst.li << 2)
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{
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// If bit 26 is 1 then sign extend
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if (disp & 0x2000000) {
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disp |= 0xfc000000;
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}
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}
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PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for unconditional, non PC-relative branches.
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*/
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class BranchNonPCRel : public PCDependentDisassembly
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{
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protected:
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/// Target address
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uint32_t targetAddr;
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/// Constructor.
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BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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targetAddr(machInst.li << 2)
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{
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// If bit 26 is 1 then sign extend
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if (targetAddr & 0x2000000) {
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targetAddr |= 0xfc000000;
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}
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}
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PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for conditional branches.
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*/
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class BranchCond : public PCDependentDisassembly
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{
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protected:
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/// Fields needed for conditions
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uint32_t bo;
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uint32_t bi;
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/// Constructor.
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BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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bo(machInst.bo),
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bi(machInst.bi)
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{
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}
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inline bool
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ctrOk(uint32_t& ctr) const
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{
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bool ctr_ok;
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if (bo & 4) {
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ctr_ok = true;
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} else {
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ctr--;
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if (ctr != 0) {
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ctr_ok = ((bo & 2) == 0);
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} else {
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ctr_ok = ((bo & 2) != 0);
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}
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}
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return ctr_ok;
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}
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inline bool
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condOk(uint32_t cr) const
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{
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bool cond_ok;
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if (bo & 16) {
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cond_ok = true;
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} else {
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cond_ok = (((cr >> (31 - bi)) & 1) == ((bo >> 3) & 1));
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}
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return cond_ok;
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}
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};
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/**
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* Base class for conditional, PC-relative branches.
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*/
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class BranchPCRelCond : public BranchCond
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{
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protected:
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/// Displacement
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uint32_t disp;
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/// Constructor.
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BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
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: BranchCond(mnem, _machInst, __opClass),
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disp(machInst.bd << 2)
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{
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// If bit 16 is 1 then sign extend
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if (disp & 0x8000) {
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disp |= 0xffff0000;
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}
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}
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PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for conditional, non PC-relative branches.
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*/
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class BranchNonPCRelCond : public BranchCond
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{
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protected:
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/// Target address
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uint32_t targetAddr;
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/// Constructor.
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BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
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: BranchCond(mnem, _machInst, __opClass),
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targetAddr(machInst.bd << 2)
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{
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// If bit 16 is 1 then sign extend
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if (targetAddr & 0x8000) {
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targetAddr |= 0xffff0000;
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}
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}
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PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for conditional, register-based branches
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*/
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class BranchRegCond : public BranchCond
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{
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protected:
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/// Constructor.
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BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
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: BranchCond(mnem, _machInst, __opClass)
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{
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}
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PowerISA::PCState branchTarget(ThreadContext *tc) const;
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/// Explicitly import the otherwise hidden branchTarget
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using StaticInst::branchTarget;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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} // namespace PowerISA
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#endif //__ARCH_POWER_INSTS_BRANCH_HH__
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