495 lines
54 KiB
Text
495 lines
54 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1455036 # Simulator instruction rate (inst/s)
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host_mem_usage 382532 # Number of bytes of host memory used
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host_seconds 35.16 # Real time elapsed on the host
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host_tick_rate 3251070052 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 51162775 # Number of instructions simulated
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sim_seconds 0.114317 # Number of seconds simulated
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sim_ticks 114316622000 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11594.610314 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits::0 95143 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 95143 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 75279000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051425 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 5158 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 5158 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 59805000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses::0 7815759 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 7815759 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.214184 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12650.891296 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits::0 7577286 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7577286 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3732392000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.030512 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 238473 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 238473 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 3016896000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030512 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 238473 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38196735000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses::0 6667481 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6667481 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.618008 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.411843 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits::0 6495289 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 6495289 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 7012970000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.025826 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 172192 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 172192 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 6496358500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025826 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 172192 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 931126000 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 34.469586 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::0 14483240 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 14483240 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 26165.760413 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 14072575 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 14072575 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10745362000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.028354 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::0 410665 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 410665 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 9513254500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.028354 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 410665 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_blocks::0 509.189203 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.994510 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses::0 14483240 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 14483240 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 26165.760413 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 23165.486467 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::0 14072575 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_hits::total 14072575 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10745362000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.028354 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::0 410665 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_misses::total 410665 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 9513254500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.028354 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 410665 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 39127861000 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 413472 # number of replacements
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system.cpu.dcache.sampled_refs 413984 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 509.189203 # Cycle average of tags in use
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system.cpu.dcache.total_refs 14269857 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 382812 # number of writebacks
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system.cpu.dtb.accesses 15512082 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 15506431 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 5651 # DTB misses
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system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 8731607 # DTB read accesses
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system.cpu.dtb.read_hits 8726923 # DTB read hits
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system.cpu.dtb.read_misses 4684 # DTB read misses
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system.cpu.dtb.write_accesses 6780475 # DTB write accesses
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system.cpu.dtb.write_hits 6779508 # DTB write hits
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system.cpu.dtb.write_misses 967 # DTB write misses
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system.cpu.icache.ReadReq_accesses::0 41483736 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 41483736 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency::0 14791.732049 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.415195 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.icache.ReadReq_hits::0 41049747 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 41049747 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 6419449000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate::0 0.010462 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses::0 433989 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 433989 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 5116910500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010462 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 433989 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 94.587068 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses::0 41483736 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 41483736 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::0 14791.732049 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency
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system.cpu.icache.demand_hits::0 41049747 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 41049747 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 6419449000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate::0 0.010462 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.icache.demand_misses::0 433989 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 433989 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 5116910500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate::0 0.010462 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 433989 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_blocks::0 484.311851 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.945922 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses::0 41483736 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 41483736 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency::0 14791.732049 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 11790.415195 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits::0 41049747 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
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system.cpu.icache.overall_hits::total 41049747 # number of overall hits
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system.cpu.icache.overall_miss_latency 6419449000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate::0 0.010462 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.icache.overall_misses::0 433989 # number of overall misses
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system.cpu.icache.overall_misses::1 0 # number of overall misses
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system.cpu.icache.overall_misses::total 433989 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 5116910500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate::0 0.010462 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 433989 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 433477 # number of replacements
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system.cpu.icache.sampled_refs 433989 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 484.311851 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 41049747 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 34328 # number of writebacks
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu.itb.accesses 41486666 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 41483736 # DTB hits
|
|
system.cpu.itb.inst_accesses 41486666 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 41483736 # ITB inst hits
|
|
system.cpu.itb.inst_misses 2930 # ITB inst misses
|
|
system.cpu.itb.misses 2930 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.numCycles 228633244 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.num_busy_cycles 228633244 # Number of busy cycles
|
|
system.cpu.num_conditional_control_insts 7015568 # number of instructions that are conditional controls
|
|
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
|
|
system.cpu.num_fp_insts 6058 # number of float instructions
|
|
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
|
|
system.cpu.num_func_calls 1109778 # number of times a function call or return occured
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu.num_insts 51162775 # Number of instructions executed
|
|
system.cpu.num_int_alu_accesses 42435662 # Number of integer alu accesses
|
|
system.cpu.num_int_insts 42435662 # number of integer instructions
|
|
system.cpu.num_int_register_reads 248572490 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 49713526 # number of times the integer registers were written
|
|
system.cpu.num_load_insts 9182978 # Number of load instructions
|
|
system.cpu.num_mem_refs 16261071 # number of memory refs
|
|
system.cpu.num_store_insts 7078093 # Number of store instructions
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
system.l2c.ReadExReq_accesses::0 170353 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 170353 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_hits::0 62556 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 62556 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 0.632786 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.632786 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 675448 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::1 6192 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 681640 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits::0 657448 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::1 6170 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 663618 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.026649 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::1 0.003553 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.030202 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::1 22 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.026682 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 2.910530 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 2.937211 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 29204423000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 72880000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990756 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 743252000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses::0 417140 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 417140 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 417140 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 417140 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 7.067586 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 845801 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 6192 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 851993 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 720004 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 6170 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 726174 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.148731 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 0.003553 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.152284 # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 125797 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 22 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 125819 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.148757 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 20.319606 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 20.468363 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_blocks::0 5338.058091 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 31318.757980 # Average occupied blocks per context
|
|
system.l2c.occ_percent::0 0.081452 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::1 0.477886 # Average percentage of cache occupancy
|
|
system.l2c.overall_accesses::0 845801 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 6192 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 851993 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 720004 # number of overall hits
|
|
system.l2c.overall_hits::1 6170 # number of overall hits
|
|
system.l2c.overall_hits::total 726174 # number of overall hits
|
|
system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.148731 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 0.003553 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.152284 # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 125797 # number of overall misses
|
|
system.l2c.overall_misses::1 22 # number of overall misses
|
|
system.l2c.overall_misses::total 125819 # number of overall misses
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.148757 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 20.319606 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 20.468363 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 29947675000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 93111 # number of replacements
|
|
system.l2c.sampled_refs 124568 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 36656.816071 # Cycle average of tags in use
|
|
system.l2c.total_refs 880395 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 87350 # number of writebacks
|
|
|
|
---------- End Simulation Statistics ----------
|