232 lines
26 KiB
Text
232 lines
26 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 290934 # Simulator instruction rate (inst/s)
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host_mem_usage 197920 # Number of bytes of host memory used
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host_seconds 0.02 # Real time elapsed on the host
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host_tick_rate 939694341 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 4833 # Number of instructions simulated
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sim_seconds 0.000016 # Number of seconds simulated
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sim_ticks 15925000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 1338000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 1230000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 562 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 2475000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.149773 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 99 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 2277000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.149773 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 99 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 24921.568627 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 22921.568627 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1116 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 3813000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.120567 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3507000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.120567 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 24921.568627 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 22921.568627 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1116 # number of overall hits
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system.cpu.dcache.overall_miss_latency 3813000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.120567 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 153 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3507000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.120567 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 83.440192 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
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system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses
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system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 4621 # number of overall hits
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system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses
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system.cpu.icache.overall_misses 256 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 114.921642 # Cycle average of tags in use
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system.cpu.icache.total_refs 4621 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 84 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 1848000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 84 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 924000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 84 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 6754000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 330000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 8602000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 3 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 8602000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 391 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 133.706132 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 31850 # number of cpu cycles simulated
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system.cpu.num_insts 4833 # Number of instructions executed
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system.cpu.num_refs 1282 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
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---------- End Simulation Statistics ----------
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